Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electrical Industrial Do., Ltd.

Yoshiro Nakata

Shinichi Oki

Susumu Matsumoto

Shozo Okada

Naoto Matsuo

Toshiki Yabu

Shin Hashimoto

Koichi Nagao

Hisashi Ogawa

Toshio Yamada

Isao Miyanaga

Akinori Shibayama

Atsushi Fujiwara

Hironori Akamatsu

Takashi Sato

Kenzo Hatada

Hiroyuki Sakai

Hisakazu Kotani

Kunio Sano

Hideya Esaki

Masaaki Ishizaka

Naomi Miyake

Keiichi Fujimoto

Noriko Tsutsu

Shigeoki Mori

The connection between a PTC elementcorresponding to each semiconductor ICand a power-supply lineis performed via a relay, a high voltage is supplied to the power-supply lineby sequentially turning on the relays, and a high voltage is supplied to each PTC elementin order, whereby it is possible to trip beforehand a PTC elementconnected to a DC-defective semiconductor IC. In this state, wafer level burn-in is performed together, which enables the PTC elementto be positively tripped during the burn-in for the DC defect of the semiconductor IC, with the result that it is possible to increase the reliability of the burn-in.

Inspection apparatus and method for semiconductor IC

A semiconductor integrated circuit testing system for testing electric characteristics of a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer in the lump includes a wafer tray for holding the semiconductor wafer and an interconnect substrate facing the semiconductor wafer held on the wafer tray and having interconnect layers to which a testing voltage is externally input. A ring-shaped sealing member is provided between the wafer tray and the interconnect substrate so as to form a sealed space together with the wafer tray and the interconnect substrate. An elastic sheet is held on the interconnect substrate at the periphery thereof. A plurality of probe terminals electrically connected to the interconnect layers are provided on the elastic sheet in positions respectively corresponding to external electrodes of the plural semiconductor integrated circuit devices. A plurality of protrusions protruding toward the wafer tray are provided on the elastic sheet for preventing the interconnect substrate from deforming toward the wafer tray when the internal pressure of the sealed space is reduced.

Semiconductor integrated circuit testing system and method

A method of testing semiconductor integrated circuits comprises the step of simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to the respective testing electrodes of the semiconductor integrated circuit elements. The simultaneous testing step includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via PTC elements provided for the semiconductor integrated circuit elements in a one-to-one relationship.

Method of testing semiconductor integrated circuits and testing board for use therein

A probe card is used in testing an electric characteristic of plural semiconductor chips formed on a semiconductor wafer in a batch at a wafer level through application of a voltage to electrodes of the semiconductor chips. The probe card includes a card body, plural probe terminals, a wiring and a control element. The plural probe terminals are disposed on one surface of the card body in positions corresponding to the electrodes of the semiconductor chips. The wiring is disposed on the other surface of the card body and electrically connected with the probe terminals. The control element is disposed on the latter surface of the card body between the wiring and the probe terminals and controls input/output of the semiconductor chips.

Probe card

A wafer tray has a wafer mount portion for carrying a semiconductor wafer formed with a plurality of semiconductor chips. A probe card composed of an elastic material and disposed in opposing relation to the wafer mount portion of the wafer tray has bumps to be connected to the respective electrode pads of the semiconductor chips on the top surface thereof. A holding board is provided to hold the back surface of the probe card. An annular sealing member is disposed on the wafer tray externally of the wafer mount portion and defines a first sealed space in combination with the wafer tray and the probe card. The probe card has connection holes for connecting the first sealed space to a second sealed space formed between the probe card and the holding board.

Wafer burn-in cassette and method of manufacturing probe card for use therein

Method of testing electrical characteristics of multiple semiconductor integrated circuits simultaneously

A probe card for wafer-level measurement comprises a plurality of bump electrodes arranged in two dimensions and a multilayer wiring board electrically connected to the bump electrodes. The multilayer wiring board has a multilayer ceramic board and a thin-film wiring layer formed by a lithographic technique. The thin-film wiring layer comprises a plurality of pads, each of which include: a via contact region for contact with a via electrode at the surface of the multilayer ceramic board; a bump contact region for contact with at least one of the probe electrode; and a lead region for providing a connection between the via contact region and the bump contact region.

Probe card for wafer-level measurement, multilayer ceramic wiring board, and fabricating methods therefor

A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.

Semiconductor integrated circuit having a plurality of chips

A 12.5-MHz signal is applied from outside a semiconductor integrated circuit (SIC) device to a signal input terminal of that SIC device. A frequency multiplying circuit is fed that 12.5-MHz signal from the input terminal, and delivers a reference signal whose frequency is a multiple of the frequency of the signal received (i.e., 100 MHz), to a semiconductor memory and to a self-test circuit. The self-test circuit provides a test signal in synchronism with that 100-MHz reference signal to the semiconductor memory for testing for the presence or absence of a failure. All elements of the semiconductor memory are tested by the self-test circuit for a failure. If the self-test circuit finds a semiconductor memory element that fails to work properly, it provides a signal indicative of such failure to a failure counting circuit. This failure counting circuit counts the number of times the self-test circuit provides such a signal.

Semiconductor integrated circuit device having failure detection

Bumps to be connected to inspection electrodes of semiconductor chips are formed on a surface of a flexible substrate. A plating layer is formed which is made of a harder material than the bumps formed on the flexible substrate and which has a concave portion or a convex portion whose diameter is equal to or smaller than half the diameter of the bumps, on a flat metallic plate. The plating layer of the metallic plate is pressed against top surfaces of the bumps, so that irregularities are formed in the top surfaces of the bumps.

Method of manufacturing probe card

A semiconductor integrated circuit apparatus having a plurality of semiconductor integrated circuit devices, each of the plurality of semiconductor devices including a semiconductor integrated circuit formed on a semiconductor substrate, a reference voltage input terminal formed on the semiconductor substrate which is operative for receiving a reference voltage input from outside of the semiconductor substrate, and a burn-in voltage control circuit formed on the semiconductor substrate operative for receiving the reference voltage which is output from the reference voltage input terminal. The burn-in voltage control circuit generates a burn-in supply voltage which is input to the semiconductor integrated circuit, and also maintains the burn-in supply voltage at the reference voltage level such that each of the integrated circuits receives a burn-in supply voltage having the same voltage level.

Semiconductor integrated circuit device

A plated layer made of a metal which is hard to oxidize is formed on the surface of a check electrode of a semiconductor chip which is formed on a semiconductor wafer. A bump of a contactor is caused to come in contact with the check electrode on which the plated layer is formed in the direction perpendicular to the semiconductor chip. Then, a voltage is applied to the bump of the contactor to make a check such as burn-in on the semiconductor chip in a lump.

Semiconductor device checking method

A semiconductor wafer is affixed on a dicing sheet having an appropriate expansibility. Then, a dicing operation is performed on the semiconductor wafer without dividing the dicing sheet, thereby dividing a plurality of semiconductor chips from each other. After aligning a contactor against the semiconductor wafer, the semiconductor wafer is fixed to the contactor. In this case, protrusions provided on the contactor are inserted into the gap between semiconductor chips. The protrusions cause a shift movement toward the peripheral edge of the contactor in response to thermal expansion of the contactor, thereby expanding the gap between semiconductor chips. Then a burn-in is performed on all of the plural semiconductor chips of which gap is expanded.

Inspecting method for semiconductor devices

A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

Growing community of inventors

Kyoto, Japan

Yoshiro Nakata