Semiconductor Components Industries, LLC

Yoshio Enosawa

Zia Hossain

Evgueniy Nikolov Stefanov

Mohamed Imam

Joe Fulton

Taku Yamamoto

Katsuya Yamazaki

Masami Tanaka

A high voltage MOSFET device ( ) has an nwell region ( ) with a p-top layer ( ) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability

A high voltage MOSFET device ( ) has a well region ( ) with two areas. The first area ( ) has a high dopant concentration and the second area ( ) has a low dopant concentration. Inside the well region a region of a secondary conductivity type ( ) is formed. The second area ( ) is typically underlying a gate region ( ). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the &ldquo;on&rdquo; state. The MOSFET device further has a p-top layer ( ) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.

Method for manufacturing a high voltage MOSFET device with reduced on-resistance

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Yoshio Enosawa