Sanyo Electric Co., Ltd.

Yoshinari Ichihashi

Yoshio Okayama

Hayato Nakashima

Takashi Goto

Norihiro Ikeda

Tatsuya Fujishima

Takashi Gotou

Ryousuke Usui

On a substrate are sequentially formed a first interconnection, a diffusion barrier filmand a second insulating film, and on the upper surface of the second insulating filmis then formed a sacrificial film. Next, a via holeand an interconnection trenchare formed, and on the sacrificial filmare then formed a barrier metal filmand a copper film. CMP for removing the extraneous copper filmand barrier metal filmare conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal filmand the second polishing where the remaining barrier metal filmand the tapered sacrificial filmare polished.

Method of manufacturing a semiconductor device

A semiconductor device capable of compatibly suppressing a microloading effect (irregular etching) and over-etching also in formation of a fine contact hole requiring a high aspect ratio is obtained. This semiconductor device comprises a first conductive part, an insulator film having an opening formed on the first conductive part and a second conductive part electrically connected with the first conductive part through the opening. The insulator film includes an upper insulator film and a lower insulator film, stacked/formed at least around a connection part between the first conductive part and the second conductive part, consisting of different materials. Thus, when employing a material having a higher etching selection ratio than the upper insulator film for the lower insulator film, the first conductive part is prevented from over-etching also when etching is performed through a high-concentration plasma device with which a high etching selection ratio of the first conductive part is hard to attain for suppressing a microloading effect (irregular etching).

Semiconductor device having opening and method of fabricating the same

A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.

Method for manufacturing semiconductor device

Growing community of inventors

Gifu, Japan

Yoshinari Ichihashi