Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Other

Renesas Solutions Corporation

Yoshikazu Miyawaki

Takeshi Nakayama

Yasushi Terada

Shinichi Kobayashi

Tomoshi Futatsuya

Masanori Hayashikoshi

Masaaki Mihara

Kazuo Kobayashi

Atsushi Ohba

Shinji Kawai

Satoshi Shimizu

Natsuo Ajika

Yuichi Kunori

Hiroshi Onoda

Minoru Ohkawa

Yasuhiro Yamamoto

Makoto Ohi

Atsushi Fukumoto

Katsumi Dosaka

Tomohisa Wada

Yasuhiko Taito

Takashi Hayasaka

Satoru Kishida

Mitsuhiro Tomoeda

Hiromi Okimoto

Shinichi Ishimoto

Daisuke Agawa

Tamiyu Kato

In the present flash memory a threshold voltage of a memory transistor to which data is written is detected and the detected value is used to set an initial value of a pulse voltage of a write pulse signal, and whenever the write pulse signal is applied, the pulse voltage is increased by a step voltage. The memory transistor's drain current and the threshold voltage's variation can be smaller than when a fixed pulse voltage is applied, as conventional.

Non-volatile semiconductor memory device with memory transistor

A memory mat is provided separately from a memory mat that is a normal memory area, and data therein cannot be read from the outside. In a page buffer, information input from the outside is stored. A comparing circuit compares security information stored in memory mat with information stored in page buffer, and the comparison result is output to the outside as a status. Even when unauthorized copying is performed, information in memory mat is not copied. Therefore, an external apparatus can easily determine whether or not the semiconductor memory is an unauthorized copy by referring to the status.

Semiconductor memory preventing unauthorized copying

Operations of applying an erase pulse and further performing block program before erasure are executed in steps S and S before applying the erase pulse on a block by block basis. This narrows the distribution width of the threshold voltage, and reduces the number of the memory transistors to be subjected to over-erase verify so that a total erasing time of data of a flash memory can be reduced.

Nonvolatile semiconductor memory device and method of erasing data of nonvolatile semiconductor memory device

A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to coincidence/non-coincidence of prescribed bits of address signals supplied from an address buffer, and the generated signal is supplied to an internal control circuit. Thus, necessary data can be read out from the non-volatile semiconductor memory device at high speed, so that usability of the device is improved.

Non-volatile memory with background operation function

Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.

Nonvolatile semiconductor memory device having reduced erase time and method of erasing data of the same

An external read sense amplifier for reading out a data to an outside and an internal verify sense amplifier for reading out a data for an internal operation are provided, separately from each other, to a plurality of banks. Preferably, an internal verify sense amplifier is provided for each prescribed number of memory blocks. There is provided a nonvolatile semiconductor memory device with a background operation function, having a reduced chip occupancy area.

Nonvolatile memory with background operation function

At the time of writing data, a tester outputs a chip enable signal /CE of the L level and selection signals of the L level to simultaneously make semiconductor memory devices active. At the time of reading data, the tester outputs the chip enable signal of the L level to the semiconductor memory devices, and selectively switches the logic level of a selection signal to be outputted to some semiconductor memory devices and that of the selection signal to be outputted to the other semiconductor memory devices to the L level. In such a manner, a number of semiconductor memory devices can be tested without increasing the number of pins of the tester.

SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY TESTED EVEN WHEN THE NUMBER OF SEMICONDUCTOR MEMORY DEVICES IS LARGE AND SEMICONDUCTOR WAFER ON WHICH THE SEMICONDUCTOR MEMORY DEVICES ARE FORMED

The semiconductor memory device receives K addresses from first to Kth addresses having at least one bit in common (where K is a natural number; K&gE;2). Each data block is divided into a plurality of sub data blocks, and a plurality of sense amplifier circuits are provided corresponding to the respective sub data blocks. In each data block, K read data are selected in response to the first address input. Each of the K read data is amplified and output by one of the plurality of sense amplifier circuits sequentially selected in response to each address input.

Semiconductor memory device having high-speed read function

A memory transistor for a lock bit, holding information on whether a memory block can be erased/reprogrammed, is provided in the same column as that of a plurality of dummy cells. Since a sub bit line for reading the lock bit is electrically isolated from a sub bit line for dummy cell, accurate lock-bit reading is possible even when the dummy cell is over erased. Thus, a nonvolatile semiconductor memory device advantageous in reliability and operation time can be provided.

Nonvolatile semiconductor memory device with improved reliability and operation speed

A voltage generation portion includes a voltage amplifier circuit, receiving a boosted potential VPP generated by a charge pump circuit to output an output potential Vout equal to a standard potential VIN. Output potentials Vout are distributed as voltages for rewriting and erasing on a flash memory via distributor. The output potential Vout can be changed faster than the boosted potential VPP generated by the charge pump circuit does.

Nonvolatile semiconductor memory device capable of high speed generation of rewrite voltage

Operations of applying an erase pulse and further performing block program before erasure are executed in steps S,and S,before applying the erase pulse on a block by block basis. This narrows the distribution width of the threshold voltage, and reduces the number of the memory transistors to be subjected to over-erase verify so that a total erasing time of data of a flash memory can be reduced.

A memory cell array is divided into a plurality of memory cell blocks each collectively subjected to an erasing operation as a unit. A P well regions for memory cell transistors and an N well region for electrically separating the P well regions are provided. Select transistors are formed in the same P well region as the memory cell transistor connected to the corresponding sub bit line of P well regions.

Nonvolatile semiconductor memory device capable of reducing memory array area

A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector. There is also disclosed semiconductor integrated circuit having a high voltage step-down circuit for outputting plural stepped-down voltages having a fine tuner for fine-tuning each of the plural stepped-down voltages wherein a stepped-down voltage having been tuned finely is compared with a reference voltage given by a reference voltage generator.

Semiconductor integrated circuit device with adjustable high voltage

A non-volatile semiconductor memory device comprises a bit line 402, a plurality of word lines 401 arranged to cross the bit line 402, a plurality of non-volatile memory cells 404 which are disposed at the crossing points of the bit line 402 and the word lines 401 and which have a drain 404a connected to the bit line 402 and a control gate 404f connected to the corresponding word line 401, and a word line potential applying means 300, 500 wherein in an ordinary reading mode, a selective potential is applied to a word line 401 selected from the plurality of word lines, while a non-selective potential, which is lower than the selective potential, is applied to unselected word lines 401 in response to an address signal, and in a prescribed mode, the selective potential is applied to a word line 401 selected from the plurality of word lines, while a prescribed potential, which is lower than the non-selective potential, is applied to the unselected word lines in response to an address signal.

Non-volatile semiconductor memory device

A high voltage generating device includes a charge pump generating high voltage by boosting a power supply voltage and supplying it to a load, a timer measuring activation time of the charge pump and outputting a signal after a prescribed time period, an A-D converter converting an output voltage of the charge pump into a digital value in response to the signal and outputting four bit binary data, and a current limiting circuit including four P channel MOS transistors connected in parallel between a power supply node and a drain of an N channel MOS transistor which has a gate receiving the digital value output from the A-D converter.

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Hyogo, Japan

Yoshikazu Miyawaki