Seiko Epson Corporation

Yoshikazu Kasuya

Katsumi Mori

Kei Kawahara

Takamitsu Higuchi

Aritsugu Yajima

A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.

Semiconductor device

Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.

A semiconductor device has first wiring layersand a plurality of dummy wiring layersthat are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines Lextending in a direction traversing the row direction. The row direction and the first virtual linear lines Ldefine an angle of 2-40 degrees, and the dummy wiring layersare disposed in a manner to be located on the first virtual linear lines L. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines Lextending in a direction traversing the column direction. The column direction and the second virtual linear lines Ldefine an angle of 2-40 degrees, and the dummy wiring layersare disposed in a manner to be located on the second virtual linear lines L

A method for manufacturing a surface acoustic wave element having an interdigital transducer (IDT) electrode formed on a semiconductor substrate includes a) forming an insulation layer on a surface of an active side of the semiconductor substrate, b) forming a base layer on a whole surface of the insulation layer, c) planarizing a surface of the base layer, d) forming a piezoelectric member on a planarized surface of the base layer, e) forming the IDT electrode on a surface of the piezoelectric member, and f) forming a bank being higher than a height from the surface of the base layer to the surface of the IDT electrode on a peripheral of the surface of the base layer so as to surround the piezoelectric member.

Method for manufacturing a surface acoustic wave element having an interdigital transducer (IDT) electrode

Semiconductor device having dummy wiring layers and a method for manufacturing the same

A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer to form a source region or a drain region; and sidewall-shaped control gates formed along both side surface of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other. The first control gate and the second control gate are respectively formed on insulating layers having different thickness.

Growing community of inventors

Sakata, Japan

Yoshikazu Kasuya