Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Renesas Technology Corp.

Yoshihisa Matsubara

Manabu Iguchi

Takashi Ishigami

Kazuhiko Endo

Toshiyuki Takewaki

Shinya Ito

Nobukazu Ito

Hiromichi Suzuki

Norio Okada

Yoshiaki Yamada

Noriaki Oda

Akira Matsumoto

Toru Tatsumi

Tadahiko Horiuchi

Seiji Kato

Ko Noguchi

Wahei Kitamura

Masato Kawata

Masahiko Nakamae

Yoshishige Matsumoto

Hiromasa Kobayashi

Kosho Akiyama

Shinichi Watanuki

Kazuyoshi Ueno

Takashi Sakoh

Kazumi Sugai

Masahiro Komuro

Takahiro Onodera

Hiroki Shirai

An improvement is achieved in the performance of a semiconductor-device. The semiconductor device includes MISFETs formed in the upper surface of a substrate, a plurality of wiring layers stacked over the upper surface of the substrate, and a plurality of plugs each coupling two of the wiring layers to each other. The wiring layers located under the uppermost wiring layer include wires. The uppermost wiring layer includes a pad, an insulating film formed over the pad, and an opening extending through the insulating film and reaching the pad. The MISFETs and the wires overlap the opening in plan view. None of the plurality of plugs overlaps the opening in plan view.

Semiconductor device and manufacturing method thereof

In a semiconductor device including a higher-breakdown-voltage MISFET, an improvement is achieved in the breakdown voltage of the MISFET, while preventing an increase in the area of the MISFET. A gate pattern including a gate electrode of the higher-breakdown-voltage MISFET is formed higher in level than a gate pattern including a gate electrode of a lower-breakdown-voltage MISFET. An n-type semiconductor region included in each of source/drain regions of the higher-breakdown-voltage MISFET is formed deeper than an n-type semiconductor region included in each of source/drain regions of the lower-breakdown-voltage MISFET.

Performance of a semiconductor device is improved. Graphene particles are mixedly added in a sealing resin covering a semiconductor chip. The graphene particles are thus mixedly added in the sealing resin, thereby thermal conduction of the sealing resin is improved, and thus radiation performance of the semiconductor device can be improved. Graphene is a sheet of spbonded carbon atoms having a monolayer thickness. Graphene has a structure where hexagonal lattices, each of which is formed of carbon atoms and bonds of the carbon atoms, are planarly spread. Graphene is preferably used as heat transfer filler because of its high thermal conductivity and light weight.

Semiconductor device

A semiconductor device including a semiconductor chip and a heat dissipation unit (heat sink) is configured as follows. The heat dissipation unit (heat sink) includes a resin tape, and a fin constituted of a graphite sheet and protruding from the resin tape. The fin, including graphene, is disposed on the semiconductor chip such that the graphene is disposed in a direction crossing a surface of the semiconductor chip. The heat dissipation unit is a rolled body in which the graphite sheet and the resin tape are layered and rolled. Thus, by use of the graphene as a constituent material of the fin, thermal conductivity is improved, whereby a heat dissipation characteristic is improved. Furthermore, since the fin is protruded from the resin tape, an exposed area of the fin is increased, and accordingly, the heat dissipation characteristic can be improved.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a substrate, a multilayer wiring layer formed over the substrate, an MTJ (Magnetic Tunnel Junction) element formed in an insulating layer located lower than an uppermost wiring layer in the multilayer wiring layer, a wiring formed in a wiring layer immediately above the MTJ element and coupled to the MTJ element, and a shield conductor region provided in the wiring or a wiring layer immediately above the wiring, and covering an entirety of the MTJ element in a plan view.

Semiconductor device and manufacturing method of the semiconductor device

A method for manufacturing a semiconductor device includes forming a first interconnect over the semiconductor substrate; forming an interlayer dielectric film over the first interconnect; forming a hole in the interlayer dielectric film such that the hole reaches the first interconnect; forming a trench in the interlayer dielectric film; and embedded a conductive film in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench, wherein, in a planar view, the first interconnect extends in a first direction, wherein, in a planar view, the second interconnect extends in a second direction which is perpendicular to the first direction, and wherein a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction.

Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same

An MTJ element is formed in a wiring layer located in a lower tier and yet application of heat to the MTJ element is suppressed. A first insulating layer is formed over a substrate. Subsequently, the MTJ element is formed over the first insulating layer. After that a first wiring is formed over the MTJ element. Thereafter, a second insulating layer is formed over the first wiring. Then a second wiring is formed in the superficial layer of the second insulating layer. The second wiring is heat treated by photoirradiation. A shield conductor is formed at the step of forming the second wiring.

A semiconductor device includes a first interconnection including a first end, a second interconnection connected to the first interconnection and including a width being gradually wider towards the first end, a third interconnection and a fourth interconnection, the third interconnection and the fourth interconnection being arranged to sandwich the second interconnection. The first interconnection, the second interconnection, the third interconnection, and the fourth interconnection are each formed in a same layer and a width of the first interconnection is wider than a width of the second interconnection.

A semiconductor device having a via chain circuit including a plurality of fine interconnections and an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the via chain circuit. One or more of the fine interconnections becomes wider gradually towards the connection to the extension interconnection. The extension interconnection is formed in a same layer as the one or more of the fine interconnections connected to the extension interconnection. The one or more of the fine interconnections connected to the extension interconnection is connected to the extension interconnections at a position where the fine interconnections become wider.

Unless layers over a TEG pattern are removed, a test using the TEG pattern is conducted. Multiple wiring layers are formed over a first TEG pattern. A wiring and multiple dummy patterns are formed in each of the wiring layers. An electrode pad is formed in an uppermost wiring layer. In a planar view, the first TEG pattern eliminates overlap with all of the wirings and the dummy patterns.

Semiconductor device, method of manufacturing the same, and method of designing the same

A semiconductor integrated circuit includes a first conductor provided in a first region on a substrate and a second conductor provided in a second region on the substrate. The second region is a region enclosing the first region. A minimum design dimension in linewidth of the first conductor is smaller than a minimum design dimension in linewidth of the second conductor.

Semiconductor integrated circuit and method for manufacturing same, and mask

A semiconductor device, including: a first transistor formed on a substrate and including an Hf contained film as its gate insulating film; and a second transistor formed on said substrate and having the same conductive type as that of said first transistor, said second transistor including a silicon oxide film and not including an Hf contained film as its gate insulating film is provided.

Semiconductor device and method of manufacturing the same

A displacement detection pattern, usable for detection of a relative displacement between a wiring and a via plug, includes a wiring provided between via plugs and a conductor. The conductor is provided in the same layer level as a level at which the wiring is provided and is provided at a predetermined distance from the wiring.

Displacement detection pattern for detecting displacement between wiring and via plug, displacement detection method, and semiconductor device

A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit, and one or more of the fine interconnections widened towards the connection to the extension wiring interconnection. The extension interconnection is formed in the same layer as one or more of the interconnections connected to the extension interconnection.

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Kanagawa, Japan

Yoshihisa Matsubara