Other

Yoshihiro Shimada

Carlos Alberto Paz De Araujo

Eiji Fujii

Yasuhiro Uemoto

Shinichiro Hayashi

Michael C Scott

Masamichi Azuma

Joseph D Cuchiaro

Akihiro Matsuda

Toru Nasu

Tatsuo Otsuki

A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100&deg; C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700&deg; C. for a barrier thickness of about 1000 &angst; and about 800&deg; C. for a barrier thickness of about 3000 &angst;. The barrier layer is 800 &angst; thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

Integrated circuit capacitors with barrier layer and process for making the same

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Kyoto, Japan

Yoshihiro Shimada