Kabushiki Kaisha Toshiba

Yoshihiro Kishita

Tatsuro Mitani

Motoki Furukawa

Toshikazu Fukuda

Kazuhiko Inoue

Souichi Imamura

Masanori Ochi

Yuji Minami

A semiconductor device which realize reduction of thickness with maintaining shielding effect has a shielding package having a substrate with a plurality of electrode pattern provided on a surface thereof and side walls upwardly formed in the peripheral end part of the surface thereof, a semiconductor chip having a plurality of electrodes directly connected to the electrode patterns of the shielding package, respectively, an insulating resin layer of a low dielectric constant formed on the substrate enclosed by the side walls so as to cover, and a conductive resin layer formed on an entire surface of the insulating resin layer.

Semiconductor device with insulating resin layer and substrate having

According to this invention, there is provided a method of manufacturing a compound semiconductor which can be formed at a high yield and in which variations in characteristics of elements caused by variations in distances between a source and a gate and between a drain and the gate can be minimized. In addition, there is provided a compound semiconductor device having a structure capable of increasing a power gain and obtaining a high-speed operation. According to this invention, an active layer is formed on a compound semi-conductor substrate, and source/drain electrodes are formed on the active layer to be separated from each other. The wall insulating films are respectively formed on side walls of the electrodes, and a gate electrode is formed between the side wall insulating films to be respectively in contact therewith.

Method of manufacturing a compound semiconductor device having gate

An integrated circuit including a wafer having a GaAs substrate, an un-doped GaAs layer, and a GaAs active layer. This active layer may have an HEMT structure to improve its operation speed. Also, the substrate may a multi-layer structure to form a three dimensional capacitor. At least one mesa portion is formed on the substrate by removing a portion of the un-doped GaAs layer and GaAs active layer. A source electrode, for example, is formed on the mesa portion, and a ground electrode is formed on an exposed surface of the substrate. These electrodes are connected to each other by means of a wiring metal layer. As a result, the source electrode is easily grounded without using a long bonding wire.

Compound semiconductor integrated circuit having improved electrode

A semiconductor device comprising a compound semiconductor substrate whose surface is provided with a source region, a drain region and an interventing channel region; a source electrode formed on said source region; a drain electrode mounted on said drain region; and a 3-ply gate electrode formed on said channel region and consisting of a high melting metal layer, a barrier metal layer and a gold layer in that order.

Semiconductor device with a 3-ply gate electrode

A GaAs semiconductor device, includes a p-type GaAs substrate, an n-type region formed in the surface area of the substrate, an ohmic contact electrode formed in ohmic contact with the n.sup.+ -type region and having a layer of alloy of gold, and an interconnection electrode formed on the ohmic contact electrode and including an upper layer of aluminum and a lower layer of a metal which prevents gold from passing through it. The interconnection electrode is formed such that it covers the top and side surfaces of the ohmic contact electrode.

GAAS semiconductor device

Disclosed is a method for forming a conductor pattern which comprises the steps of forming a conductive layer on a semiconductor substrate, forming a photoresist film on the conductive layer, removing that portion of the photoresist film located on a conductor pattern forming region of the conductive layer, forming a first masking metal film over the whole surface of the resultant structure, removing the photoresist film along with that portion of the first masking metal film formed thereon so that a portion of the first masking film remains on the conductor pattern forming region of the conductive layer to form a first masking metal pattern, and selectively removing the conductive layer by anisotropic etching to form the conductor pattern. Since the selective removal of the conductor layer is accomplished by the use of the metal pattern as a mask, it is possible to form a much finer conductor pattern than is obtained with the use of the photoresist pattern as the mask.

Method for forming a conductor pattern using lift-off

A method of forming an electrode pattern on a surface of a semiconductor substrate which comprises the steps of forming a metal film which is vulnerable to a reactive ion etching on a surface of the semiconductor substrate, forming on the metal film another metal film which is vulnerable to an ion milling but is resistant to the reactive ion etching, forming a resist pattern on the another metal film, selectively etching the another metal film by the ion milling using the resist pattern as a mask, and selectively etching the metal film by the reactive ion etching using the another metal film as a mask. A semiconductor device having an electrode pattern as formed by the above method is also disclosed.

Growing community of inventors

Kawaguchi, Japan

Yoshihiro Kishita