Fuji Electric Co., Ltd.

Fuji Electric Holdings Co., Ltd.

Yoshihiko Nagayasu

Tatsuhiko Fujihira

Naoto Fujishima

Akio Kitamura

Akihiko Ohi

Kazutoshi Sugimura

Daisuke Kishimoto

Yoichi Ryokai

Hitoshi Kuribayashi

Taku Furuta

Yuji Sano

In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 &#x3bc;m or narrower in width and even when the trenches are 1 &#x3bc;m or narrower in width.

Method for manufacturing a semiconductor device having trenches defined in the substrate surface

A field effect transistor utilizes an oxide film to obtain satisfactory performance characteristics and ease of manufacture. The field effect transistor includes a gate over a silicon substrate. The gate of the field effect transistor consists of an oxide film on the silicon substrate, a ferroelectric film on the oxide film, and an electrode metal film on the ferroelectric film. The material and the thickness of ferroelectric film are selected such that the product of the relative dielectric constant of ferroelectric film and the electric field across ferroelectric film is less than 15.6 Mv/cm. The ferroelectric film is easily formed on the oxide film. An electric filed across the oxide film of more than 4 MV/cm will result in a break down in the oxide layer. By employing a ferroelectric film with a low relative dielectric constant, the applied electric field across the oxide film is less than 4 Mv/cm. In another embodiment of the invention, a gate includes an oxide layer, an intermediate layer on the oxide layer and a ferroelectric layer on the oxide layer. The intermediate layer provides an improvement to the crystallinity of the ferroelectric layer which results in enhanced performance to the transistor, for example the turn-on voltage. The intermediate layer consists of a titanium layer on a platinum layer. The platinum layer is formed on the oxide layer to prevent the intermediate layer from peeling away from the oxide layer. The titanium layer improves the crystallinity of the ferroelectric layer.

Field effect transistor

In a method of manufacturing a semiconductor device, an insulating film is formed on a surface of a p-type semiconductor region, and then removed from a selected portion of the p-type semiconductor region. An n-type region having a high concentration of arsenic atoms is formed in a surface layer of the selected portion of the p-type semiconductor region from which the insulating film is removed. Subsequently, boron ions are implanted over an entire surface of the device in a concentration that is lower than that of the n-type region and higher than that of the p-type semiconductor region, to a smaller depth than that of the n-type region, and heat treatment is then effected to form a high-concentration boron diffused region in a surface layer of the p-type semiconductor region. An insulating film on the n-type region and an insulating film on the boron diffused region are selectively removed, and a metallic film is formed on an exposed surface of the n-type region and an exposed surface of the boron diffused region.

Method of manufacturing semiconductor device having low contact

The invention increases withstand voltage and current capacity of a DMOS portion simultaneously built in by the BiCMOS process. The manufacturing method for the DMOS portion is comprised of steps of forming an ion-implanted layer in a surface of a P-type well; forming a gate electrode; self-aligning a P-type base region by employing the P-type base formation process of the bipolar transistor and by using the gate electrode as a mask; forming a side wall on a side face of the gate electrode by employing the process for forming the LDD structure of the CMOS; and self-aligning an N+type source region by employing the process for forming the N+type source and the drain of the CMOS and by using the side wall as a mask. The effective channel length becomes longer by the side wall length and the rate of heavily doped channel portion to the total channel length becomes high. The manufacturing method effectively suppresses surface punch through by the high rate of the heavily doped channel portion and facilitates increasing withstand voltage and current capacity of the DMOS portion even when the total acceptor amount in the ion-implanted layer is insufficient.

Semiconductor apparatus manufacturing method employing gate side wall

A low-concentration region is formed by ion implanting a P-well with P.sup.+ using a gate as a mask, then an N-well is ion-implanted with As.sup.+ and B.sup.+ using a resist film and the gate as a mask to form a DMOSFET having a double-diffused drain structure. Then, the gate and an insulation material are used as a mask to ion-implant the P-well with As.sup.+ to form a CMOSFET having a lightly doped drain structure. After that, the N-well is ion-implanted with BF.sub.2.sup.+ through an opening to connect a P base region with a P base-contact region. The source/drain and p-base regions of the DMOS device are formed deeper than those of the CMOS device. Incorporation of a bipolar transistor is also disclosed. All devices are formed on the same substrate.

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Nagano, Japan

Yoshihiko Nagayasu