Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Osaka University

Panasonic Holdings Corporation

Communications Research Laboratory, Ministry of Posts and

Yoshiharu Anda

Tetsuzo Ueda

Tsuyoshi Tanaka

Mitsuru Nishitsuji

Akiyoshi Tamura

Mitsuru Tanabe

Satoshi Nakazawa

Naohiro Tsurumi

Daisuke Ueda

Manabu Yanagihara

Yoshiaki Kato

Satoshi Tamura

Yusuke Kinoshita

Toshinobu Matsuno

Katsuhiko Kawashima

Ryo Kajitani

Akihiko Nishio

Kaoru Inoue

Yasuhiro Yamada

Takahiro Yamada

Daisuke Shibata

Heiji Watanabe

Takayoshi Shimura

Takuji Hosoi

Katsunori Nishii

Hidekazu Umeda

Kazuhiro Kaibara

Asamira Suzuki

Toshiaki Matsui

Mikito Nozaki

Hong-An Shih

Nobumitsu Hirose

A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.

Semiconductor device

A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 &#x3bc;m.

Semiconductor device and method for fabricating the same

An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.

A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer.

Nitride semiconductor device and method for manufacturing nitride semiconductor device

A Schottky diode has: a semiconductor layer stack including a GaN layer formed over a substrate and an AlGaN layer formed on the GaN layer and having a wider bandgap than the GaN layer; an anode electrode and a cathode electrode which are formed at an interval therebetween on the semiconductor layer stack; and a block layer formed in a region between the anode electrode and the cathode electrode so as to contact the AlGaN layer. A part of the anode electrode is formed on the block layer so as not to contact the surface of the AlGaN layer. The barrier height between the anode electrode and the block layer is greater than that between the anode electrode and the AlGaN layer.

Schottky diode

A field effect transistor includes a nitride semiconductor multilayer structure formed on a substrate, a source electrode, a drain electrode, a gate electrode, an insulating film formed on the nitride semiconductor multilayer structure, and a field plate formed on and in contact with the insulating film, and having an end located between the gate electrode and the drain electrode. The insulating film includes a first film, and a second film having a dielectric breakdown voltage lower than that of the first film, and a thin film portion formed between the gate electrode and the drain electrode is formed in the insulating film. The field plate covers the thin film portion, and is connected to the source electrode in an opening.

Field effect transistor

A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

Nitride semiconductor device

A nitride semiconductor device includes: first electrode interconnect layers extending in parallel with one another over the nitride semiconductor layer and divided by areas extending across a longitudinal direction of the first electrode interconnect layers; first gate electrodes extending along the first electrode interconnect layers; first gate electrode connecting interconnects extending in associated ones of the areas dividing the first electrode interconnect layers and being in connection to the first gate electrodes; first electrode connecting interconnects formed above the first gate electrode connecting interconnects and being in connection to the first electrode interconnect layers; a first electrode upper interconnects formed on the first electrode connecting interconnects with an interconnect insulating film interposed therebetween, and being in connection to the first electrode connecting interconnects through associated ones of openings of the interconnect insulating film.

A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface.

A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.

Semiconductor device and manufacturing method thereof

A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.

Semiconductor device and manufacturing method of the same

There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.

Field effect transistor and method of manufacturing the same

A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate, a GaAs buffer layerthat is formed on the semi-insulating GaAs substrate, AlGaAs buffer layer, a channel layer, a spacer layer, a carrier supply layer, a spacer layer, a Schottky layercomposed of an undoped InGaP material, and an n-type GaAs cap layerA gate electrodeis formed on the Schottky layer, and is composed of LaBand has a Schottky contact with the Schottky layer, and ohmic electrodesare formed on the n-type GaAs cap layer

Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof

A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substratea GaAs buffer layerthat is formed on the semi-insulating GaAs substrateAlGaAs buffer layera channel layera spacer layera carrier supply layera spacer layera Schottky layercomposed of an undoped InGaP material, and an n-type GaAs cap layerA gate electrodeis formed on the Schottky layerand is composed of LaBand has a Schottky contact with the Schottky layerand ohmic electrodesare formed on the n-type GaAs cap layer

Pseudomorphic high electron mobility transistor with Schottky electrode including lanthanum and boron, and manufacturing method thereof

A high frequency apparatus includes a dielectric substrate having a surface including a first area and at least one second area; a first dielectric thin layer provided on a portion of a first area; and a uniplanar transmission line provided on the first dielectric thin layer and on a portion of the second area, the uniplanar transmission line extending, continuously on the second area and the first dielectric thin layer.

Growing community of inventors

Osaka, Japan

Yoshiharu Anda