Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Micron Technology Incorporated

Other

Fujitsu Limited Kabushiki Kaisha Toshiba

Yoshiaki Fukuzumi

Hideaki Aochi

Masaru Kito

Ryota Katsumata

Hiroyasu Tanaka

Masaru Kidoh

Megumi Ishiduki

Yosuke Komori

Tomoko Fujiwara

Ryouhei Kirisawa

Yasuyuki Matsuoka

Junya Matsunami

Yoshimasa Mikajiri

Shigeto Oota

Masaki Tsuji

Jun Fujiki

Mitsuru Sato

Akihiro Nitayama

Tadashi Kai

Yusuke Kohyama

Yoshihiko Kamata

Shuji Tanaka

Yoshihisa Iwata

Koji Asakawa

Masahiko Nakayama

Hideyuki Nishizawa

Shinya Arai

Hirofumi Morise

Masanobu Saito

Shigeki Hattori

Masaya Terai

Sumio Ikegawa

Masashi Yoshida

Takeshi Imamura

Tatsuya Kishi

Toshihiko Nagase

Takayuki Okada

Paolo Tessariol

Richard J Hill

Tsukasa Tada

Hiroaki Yoda

Hideaki Fukuzawa

Akira Kikitsu

Ichiro Mizushima

Naoki Yasuda

Shinji Mori

Tomoharu Tanaka

Satoshi Mikoshiba

Shiho Nakamura

Reika Ichihara

Tsuyoshi Kondo

Fumiki Aiso

Hiroyuki Nitta

Tomoo Hishida

Hiroyuki Fuke

Kiyotaro Itagaki

Koichi Kawai

Kenichiro Yoshii

Shunji Nakamura

Takuya Shimada

Matthew J King

Kazushige Kawasaki

Tomoya Sanuki

Emilio Camerlenghi

Akiyoshi Hatada

Lars P Heineck

Yoshio Ozawa

David H Wells

Atsushi Fukumoto

Yoshiaki Asao

Ching-Huang Lu

Masumi Saitoh

Kenji Tsuchida

Hiroshi Kanno

Tsuneo Inaba

Lifang Xu

Kazuyuki Higashi

Takeshi Kajiyama

Indra V Chary

Naomi Shida

Tomoko Ogura Iwasaki

Kiyotaka Miyano

David A Daycock

Hajime Nagano

Kunal Shrotri

Collin Howder

Akira Goda

Masakazu Yamagiwa

Shigeki Takahashi

Adam L Olson

Kenji Todori

Mitsuhiro Omura

Reiko Yoshimura

Takeshi Hioka

Chandra S Tiwari

Albert Fayrushin

Hiroki Yamashita

Erwin E Yu

Pitamber Shukla

Umberto Maria Meotto

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Semiconductor memory device having a circuit chip bonded to a memory array chip and including a solid-state drive controller and a control circuit

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Nonvolatile semiconductor memory device and manufacturing method thereof

A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

Microelectronic devices, and related memory devices and electronic systems

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Nonvolatile semiconductor memory device and method for manufacturing same

According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Non-volatile memory device

Semiconductor memory device having a contact plug electrically connected to an interconnection through a narrower via

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

Nonvolatile semiconductor memory device and method for driving same

An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

Electronic devices comprising multilevel bitlines, and related methods and systems

According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

Non-volatile memory device including a contour of an insulation film, located below a vertically oriented embedded body, having expanded portion corresponding to the second semicondutor portion of the lower structure

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a plurality of sets of field-effect transistors with each of the sets of field-effect transistors between the data line and a respective string of series-connected memory cells and having N field-effect transistors that are fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions, and N select lines that are each connected to a control gate of a respective field-effect transistor of each of the sets of field-effect transistors.

Apparatus containing memory array structures having multiple sub-blocks

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

Memory device including in-tier driver circuit

A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Semiconductor memory device and method for manufacturing the same

Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

Methods of forming integrated circuit structures for capacitive sense NAND memory

A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

Adaptive erase pulse width modulation based on erase suspend during erase pulse ramping period

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Yokohama, Japan

Yoshiaki Fukuzumi