Samsung Electronics Co., Ltd.

Yoon-Joo Eom

Joon-Young Park

Yongcheol Bae

Junghwan Choi

Seungjun Bae

Won Young Lee

Joosun Choi

Seongjin Jang

Hye Jung Kwon

Young-Ju Kim

Seung-Jun Bae

Young-Jin Jeon

Dae-Sik Moon

Yong-cheol Bae

Young-Chul Cho

Young-Sik Kim

Minsu Ahn

Chang-Kyo Lee

Byongmo Moon

Yongjae Lee

Min-Su Ahn

Suyeon Doo

Jun-Ha Lee

Young-ju Kim

A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

Memory device and operation method thereof

An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

Multi channel semiconductor device having multi dies and operation method thereof

Memory device and method with data input

A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.

Memory modules, memory systems including the same, and methods of calibrating multi-die impedance of the memory modules

A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

A multi channel semiconductor device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

Buffer circuit robust to variation of reference voltage signal

An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.

Output circuit for implementing high speed data transmition

An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information.

Integrated circuit with on die termination and reference voltage generation and methods of using the same

An input data alignment circuit includes a data sampler, a frequency divider, a polarity determination block, and a data alignment block. The data sampler provides a data sequence based on data serially input according to a data strobe signal. The frequency divider generates a data alignment signal based on a divided frequency of the data strobe signal. The polarity determination block determines a polarity of the data alignment signal and provides a control signal based on the determined polarity. The data alignment block aligns the data sequence in parallel according to data alignment signal and control signal and generates output data.

Input data alignment circuit and semiconductor device including the same

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

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Hwaseong-si, South Korea

Yoon-Joo Eom