Samsung Electronics Co., Ltd.

Yoo-Sang Hwang

Dae-Ik Kim

Bong-Soo Kim

Hyeong-sun Hong

Je-min Park

Je-Min Park

Hyun-Woo Chung

Sung-Hee Han

Ji-Young Kim

Ki-Seok Lee

Hui-Jung Kim

Eun-Jung Kim

Yong-kwan Kim

Yong-Chul Oh

Gyo-young Jin

Tae-jin Park

Tae-Young Chung

Byung-Jun Park

Hyoung-sub Kim

Gwan-Hyeob Koh

Jin-bum Kim

Ki-nam Kim

Jae-kyu Lee

Se-Myeong Jang

Nak-jin Son

Sung-woo Kim

Ki-seok Suh

Chan-Sic Yoon

Min-Hee Cho

Jeong-Sic Jeon

Jong-Seo Hong

Won-suk Yang

Tae Young Chung

Byung Jun Park

Dong-Hwa Kwak

Hong-sik Jeong

Young-Seung Cho

Sang-Ho Song

Cheol-ho Baek

Chun-Suk Suh

Hyeon-Ok Jung

Sung-Kwan Choi

Bomg-Soo Kim

Hyung-woo Chung

Ki-Nam Kim

Kang-Uk Kim

Cheol-Ju Yun

Sung-Un Kwon

Myeong-Dong Lee

Sung-Ho Jang

Hong-Sik Jeong

Kyung-Eun Kim

Ho-in Ryu

In-Seak Hwang

Augustin Jinwoo Hong

Jay-Bok Choi

Kyu-pil Lee

Hyun-Chul Yoon

Dong-Soo Woo

Dong-Won Shin

Byung-Hyun Lee

Jin-Hwan Chun

Si-Youn Kim

Hoon Jung

Yoon-soo Chun

Jong-Un Kim

Hyung-Soo Uh

Seok-Hyun Lim

Ye-Ro Lee

Byung Hyun Lee

Ah-Young Kim

Min-Su Choi

Jun-Hyeok Ahn

Young-Sik Seo

Tae-Yong Song

Dong-Min Han

Seok-Soon Song

Seung-young Son

Kyu-Hynn Lee

Keun-nam Kim

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Integrated circuit devices and methods of manufacturing same

A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Semiconductor devices

A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

Device comprising 2D material

An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Method of forming an integrated circuit device including a lower electrode on a sidewall of a support column extending vertical on a top surface of a substrate, a dielectric layer surrounding the support column and the lower electrode, and an upper electrode surrounding the dielectric layer

A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.

Semiconductor device for improving device characteristics

Integrated circuit devices

A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.

Semiconductor device having air gap spacer and method of fabricating the same

Integrated circuit device including a support pattern, a lower electrode pattern, a dielectric structure, and an upper electrode structure

A method of fabricating a device including a two-dimensional (2D) material includes forming an amorphous transition metal oxide structure on a substrate and replacing the amorphous transition metal oxide structure by a transition metal dichalcogenide structure. The transition metal dichalcogenide structure includes atomic layers, that are substantially parallel to a surface of the transition metal dichalcogenide structure.

Method of fabricating device including two-dimensional material

An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.

A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.

Semiconductor memory device

Integrated circuit devices including separate memory cells on separate regions of individual substrate

A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

Semiconductor device including a bit line

Growing community of inventors

Suwon-si, South Korea

Yoo-Sang Hwang