Samsung Electronics Co., Ltd.

Sansumg Electronics Co., Ltd.

Yonghwan Kwon

Taeje Cho

Seung-Kwan Ryu

Sungwoo Park

Chajea Jo

Yun Seok Choi

Yongjin Park

Woojae Kim

Sangjoon Lee

YoungHoon Ro

Hyeonji Lee

Jung-Hwan Kim

Jae Julien

Chungsun Lee

Hyuekjae Lee

Joonsung Kim

Seokhyun Kim

Hyunsoo Yuk

Sanguk Kim

Sangjin Han

Sun-Hee Park

Eunjin Lee

Taeeun Kim

Chiyoung Lee

Boin Noh

Sayoon Kang

Junggeun Kim

SangJoon Lee

HanShin Youn

Woonseong Kwon

Soyoung Shin

Hajeong Yun

Jong Yun Myung

Han-shin Youn

Jisoo Yoon

A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.

Semiconductor package and method for manufacturing semiconductor package

Disclosed is a semiconductor package comprising a semiconductor chip, a redistribution pattern on a bottom surface of the semiconductor chip and coupled to the semiconductor chip, a protection layer that covers a bottom surface of the redistribution pattern, a conductive pattern on a bottom surface of the protection layer and coupled to the redistribution pattern, a buffer pattern in contact with a bottom surface of a first part of the conductive pattern and with the bottom surface of the protection layer, and an under bump pattern on a bottom surface of the second part of the conductive pattern and covering a bottom surface and a side surface of the buffer pattern. The under bump pattern is coupled to the second part of the conductive pattern.

Semiconductor package

An electronic device includes a display and a processor configured to control the display to display a user interface (UI) screen including a plurality of graphical user interface (GUI) items and a focus GUI, identify, based on a wheel input of a user, arrangement information about the plurality of GUI items, identify, based on the arrangement information, a possible movement direction of the focus GUI displayed at a location corresponding to one GUI item among the plurality of GUI items, based on the identified possible movement direction of the focus GUI including both a horizontal direction and a vertical direction, identify a movement direction of the focus GUI as the horizontal direction, and control the display to move the focus GUI based on a manipulation direction of the wheel input and the identified movement direction.

Electronic apparatus and controlling method thereof

A semiconductor package includes a semiconductor chip on a first redistribution substrate, a molding layer that covers the semiconductor chip, and a second redistribution substrate on the molding layer and that includes a dielectric layer, a redistribution pattern, and a conductive pad. The dielectric layer includes a lower opening that exposes the conductive pad, and an upper opening connected to the lower opening and that is wider than the lower opening. The semiconductor package also comprises a redistribution pad on the conductive pad and that covers a sidewall of the lower opening and a bottom surface of the upper opening. A top surface of the dielectric layer is located at a higher level than a top surface of the redistribution pad. The top surface of the redistribution pad is located on the bottom surface of the upper opening.

A semiconductor package may include a redistribution substrate including first and second surfaces opposite each other, a first semiconductor chip on the first surface, a first molding portion on a side surface of the first semiconductor chip, a second semiconductor chip between the first semiconductor chip and the redistribution substrate, a second molding portion between the redistribution substrate and the first molding portion and on a side surface of the second semiconductor chip, bump patterns between the second semiconductor chip and the redistribution substrate, and a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate. The redistribution substrate may include first and second redistribution patterns sequentially in an insulating layer. The mold via may contact the second redistribution pattern, and the bump patterns may contact the first redistribution pattern.

A semiconductor package includes a semiconductor chip having first and second contact pads that are alternately arranged in a first direction; an insulating film having first openings respectively defining first pad regions of first contact pads, and second openings respectively defining second pad regions of the second contact pads; first and second conductive capping layers on the first and second pad regions, respectively; and an insulating layer on the insulating film, and having first and second contact holes respectively connected to the first and second conductive capping layers. Each of the first and second pad regions includes a bonding region having a first width and a probing region having a second width, greater than the first width, and each of the second pad regions is arranged in a direction that is opposite to each of the plurality of first pad regions.

Semiconductor packages

A fan-out semiconductor package includes: a support wiring structure including a support wiring conductive structure, a plurality of support wiring insulating layers including a first support wiring insulating layer having a recess area and a second support wiring insulating layer on the first support wiring insulating layer and enveloping the support wiring conductive structure, a pad layer enveloped by the second support wiring insulating layer and connected to the support wiring conductive structure, and an under-bump metallurgy (UBM) layer enveloped by the first support wiring insulating layer and connected to the pad layer; and a semiconductor chip on the support wiring structure, wherein the UBM layer includes a body portion and a protrusion protruding from the body portion and arranged in the recess area.

Fan-out semiconductor package including under-bump metallurgy

Provided is a display apparatus including: a display; a content interface; a communication interface; and a controller configured to: control the display to display an image corresponding to the broadcast signal received through the content interface; receive operation information of an external audio apparatus through at least one interface selected from the content interface and the communication interface; and control the display to display a control menu for providing the operation information of the external audio apparatus and acquiring a user input related to an operation of the external audio apparatus in response to the operation information of the external audio apparatus being received.

Display apparatus and method of controlling the same

A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure.

Semiconductor package including a chip pad having a connection portion and test portion in a first surface of the chip pad

A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.

Semiconductor package including a redistribution structure

A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member on the redistribution substrate, a second redistribution layer on an upper surface of the first molding member and having a redistribution pad, an electrical connection pad on an upper surface of a second molding member and electrically connected to the second redistribution layer, and a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer, including a first metal, and a contact layer on the conductor layer and including a second metal. The redistribution pad includes a third metal, different from the first metal and the second metal. The portion of the electrical connection pad, exposed by the opening, has a width greater than a width of the redistribution pad.

Display screen or portion thereof with graphical user interface

Growing community of inventors

Suwon-si, South Korea

Yonghwan Kwon