Samsung Electronics Co., Ltd.

Yongho Ha

Sangjin Hyun

Weonhong Kim

Yuichiro Sasaki

Seungha Oh

Sungkeun Lim

Pil-Kyu Kang

Jihye Yi

Kughwan Kim

Hyunjo Kim

Pilkyu Kang

Sang Woo Lee

Bongjin Kuh

Musarrat Hasan

Gabjin Nam

Geonju Park

A ferroelectric memory device according to the inventive concept includes a substrate having source/drain regions, an interface layer on the substrate, a high dielectric layer on the interface layer, a ferroelectric layer on the high dielectric layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures.

Ferroelectric memory device

A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

Three-dimensional semiconductor devices

An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

Method of manufacturing an integrated circuit device

A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Semiconductor device

Integrated circuit device and method of manufacturing the same

A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area can be a sidewall of one of the electrodes, or a perimeter edge of a contact opening through the electrode. Thus, when the thickness of the electrode is relatively thin, the contact area between the electrode and the phase changeable material pattern is relatively very small. As a result, it is possible to reduce power consumption of the phase changeable memory device and to form reliable and compact phase changeable memory cells.

Phase changeable memory devices

Phase changeable memory cells and methods of fabricating the same

Phase changeable memory cells

Growing community of inventors

Suwon-si, South Korea

Yongho Ha