Stats Chippac Pte. Ltd.

YongHee Kang

KiYoun Jang

Sungsoo Kim

SungWon Cho

JoonYoung Choi

Hyung Sang Park

HunTeak Lee

OhHan Kim

KyungHoon Lee

KyungOe Kim

YoungChul Kim

KeonTaek Kang

SeongBo Shim

A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.

Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding

A semiconductor device has a substrate with a first and second recess formed in a surface of the substrate using a wet etch process. The second recess can have a size different from a size of the first recess. A plurality of conductive vias are formed in a surface of the first and second recesses using a dry etch process. A first conductive layer is formed over the surface of the substrate, over curved side walls of the first and second recesses, and electrically connected to the plurality of conductive vias. A first and second semiconductor die are mounted into the first and second recesses respectively. The second semiconductor die can have a size different from a size of the first semiconductor die. The first and second semiconductor die are electrically connected to the first conductive layer. An interconnect structure is electrically connected to the plurality of conductive vias.

Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integration

A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate

A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.

Semiconductor device and method of forming a thermally reinforced semiconductor die

A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers

A method of making a semiconductor device comprises providing a carrier, forming a first conductive layer extending above a surface of the carrier, providing a substrate, disposing the first conductive layer into a first surface of the substrate, removing the carrier, forming a second conductive layer extending above the first surface of the substrate to create a vertical offset between the first conductive layer and second conductive layer, and forming a plurality of first bumps over the first conductive layer and second conductive layer. The method further includes the steps of disposing a third conductive layer into a second surface of the substrate opposite the first surface of the substrate, forming a fourth conductive layer extending above the second surface of the substrate to create a vertical offset between the third conductive layer and fourth conductive layer, and forming a plurality of second bumps.

Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers

A method of making a semiconductor device comprises forming a first conductive layer recessed below a surface of a substrate. The method further comprises forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers. The method further comprises forming an interconnect structure on the first and second conductive layers.

A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.

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Kyoung-gi-Do, South Korea

YongHee Kang