International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Yongan Xu

Yann Mignot

Hsueh-Chung Chen

Ekmini Anuja De Silva

Junli Wang

Xuefeng Liu

Yunpeng Yin

Kangguo Cheng

Peng Xu

Chi-Chun Liu

Muthumanickam Sankarapandian

Lawrence Alfred Clevenger

Oleg Gluschenkov

Dongbing Shao

John Christopher Arnold

Joe Lee

Yann A M Mignot

Fee Li Lie

Hosadurga K Shobha

Robert C Wong

Sean David Burns

Yann Alain Marcel Mignot

Hong He

Su Chen Fan

Cornelius Brown Peethala

Cheng Chi

Shyng-Tsong Chen

James John Kelly

Ailian Zhao

Chih-Chao Yang

Ruqiang Bao

Zhenxing Bi

Terry Allen Spooner

Kafai Lai

Wenhui Wang

Jing Guo

Hao Tang

Victor W C Chan

Richard C Johnson

Isabel C Estrada-Raygoza

Sylvie M Mignot

Indira P V Seshadri

Daniel J Vincent

Chanro Park

Sivananda K Kanakasabapathy

Zheng Xu

Xunyuan Zhang

Ashim Dutta

Nelson M Felix

Chiahsun Tseng

Lei Sun

Yong Liang

Karen Elizabeth Petrillo

Somnath Ghosh

Yi Song

Martin Burkhardt

Abraham Arceo De La Pena

Jennifer Fullam

Craig D Higgins

Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

Back-end-of-line single damascene top via spacer defined by pillar mandrels

A photoresist is developed on a semiconductor wafer. The wafer is introduced into a controlled cold temperature environment and is maintained there until inelastic thermal contraction of the developed photoresist material results in reducing the critical dimension (CD) of the photoresist by not less than 10% from its value before exposure to the controlled cold temperature environment. Then the semiconductor wafer is removed from the controlled cold temperature environment.

Reducing line edge roughness and mitigating defects by wafer freezing

First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

Metal via structure

Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

Developer critical dimension control with pulse development

A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

Direct extreme ultraviolet lithography on hard mask with reverse tone

A method of forming a BEOL interconnect structure having improved resistance-capacitance is provided in which a via metal layer is created by a first metallization process and thereafter shrunk by a subtractive etch; these steps relax the critical dimension, ensure a via straight profile, avoid via chamfering and bowing, and maximize metal volume. Top trench metallization is then performed above the via metal layer; this step eliminates reactive ion etch lag and ensures no metallization void issues.

Method of forming a BEOL interconnect structure using a subtractive metal via first process

A method includes applying a first metallic layer having a first metallic material onto a substrate of a semiconductor component. The method further includes removing portions of the first metallic layer to form a first metallic line. The method further includes creating an opening in the first metallic line. The method also includes depositing a dielectric material on the substrate. The method further includes forming at least one trench in the dielectric material. The method also includes depositing a second metallic material within the at least one trench to form a second metallic line. At least the first and second metallic lines and the dielectric material form an interconnect structure of the semiconductor component.

Cut integration for subtractive first metal line with bottom up second metal line

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Selective gas etching for self-aligned pattern transfer

A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.

Multiple patterning scheme integration with planarized cut patterning

A method for fabricating a semiconductor device includes forming first and second interconnect levels on a substrate with the first and second interconnect levels having respective first and second dielectric layers and first and second patterned metal conductors and where each of the first and second patterned metal conductors includes a first metallic material, depositing a third dielectric layer onto the second first interconnect layer, forming a via opening extending through the third dielectric layer and the second dielectric layer and connecting with the first patterned metal conductor of the first interconnect level and depositing a second metallic material different from the first metallic material into the via opening to form a via The via electrically couples with the patterned metal layer of the first interconnect level.

A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

Extreme ultraviolet (EUV) mask stack processing

A technique relates to a semiconductor device. Mandrels are formed on a substrate, the mandrels including a first metal layer. A second metal layer is formed on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.

Double metal patterning

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Niskayuna, NY, United States of America

Yongan Xu