Micron Technology Incorporated

Aptina Imaging Corporation

Yong Poo Chia

Suan Jeung Boon

Meow Koon Eng

Siu Waf Low

Swee Kwang Chua

Yong Loo Neo

Wei Zhou

Suangwu Huang

Tongbi T Jiang

Bok Leng Ser

Low Siu Waf

Eng Meow Koon

Chua Swee Kwang

Shuang Wu Huang

Wuu Yean Tay

Min Yu Chan

Neo Yong Loo

Yong Kian Tan

Sui Waf Low

Swee Kang Chua

Soon Huat Goh

A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.

Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an 'L' shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a 'C' shape and include a tiered portion that projects towards the lateral side of the second casing.

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Packaged microelectronic components

Growing community of inventors

Singapore, Singapore

Yong Poo Chia