Samsung Electronics Co., Ltd.

Yong-Je Lee

Won-Gil Han

Byong-Joo Kim

Seung-Weon Ha

Jae-Heung Lee

Sung-Il Cho

Ho-Tae Jin

Han-Ki Park

Seung-Lo Lee

Se-Yeoul Park

A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Method of manufacturing multi-chip package

Multi-chip package and method of manufacturing the same

A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion. The apparatus further includes a first temperature sensing unit positioned to be located at a first height and to determine a first temperature at the first portion of the stack, a second temperature sensing unit positioned to be located at a second height and to determine a second temperature at the second portion of the stack, and a temperature adjusting unit configured to compare the first temperature to the second temperature and to adjust the magnitude of the heat supplied by at least one of the heater block and the chip heating unit according to a result of the comparison.

Growing community of inventors

Hwaseong-si, South Korea

Yong-Je Lee