Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Yong-hoon Kim

Hee-Seok Lee

Seong-Ho Shin

In-Ho Choi

Jong-joo Lee

Kil-soo Kim

Kyung-suk Oh

Keung-beum Kim

Un-Byoung Kang

Heung-Kyu Kwon

Seung-Yong Cha

Tae-Hong Min

Yun-Hee Lee

Yun-Seok Choi

Se-Ho You

Jae-Choon Kim

Tae-joo Hwang

Hyo-Soon Kang

Hang-woo Lee

Jin-ha Jeong

Ji-chul Kim

Young-Don Choi

Yun-seok Choi

Ji-hyun Lee

Hyun-ki Kim

Dong-Geun Lee

Mi-Hyun Son

Jin-Kyung Kim

Joo-Hwan Chun

Jin-hong Park

Byung-Tae Yoon

Song-cheol Hong

Jin-Ha Jeong

Jae-Hun Lee

Byeong-yeon Cho

Ji-Chul Kim

Seong-yong Moon

Kwang-soo No

Jong-Wook Zeong

Hee-Seong Yang

Jang-Ho Cho

Sang-Hyouk Choi

Sang-Youb Lee

Jin-kyung Kim

Se-Min Kwak

An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

Semiconductor device package

An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Image sensor package having multi-level stack structure

Electronic device including semiconductor device package

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

Semiconductor package

A semiconductor device may include: a substrate; a first well region formed on the substrate; a second well region formed on the substrate, the first well region and the second well region extending in a first direction and being adjacent to each other in a second direction crossing the first direction; a first active region formed in the first well region; a first power region formed in the first well region, the first active region and the first power region being separate from each other in the first direction; a second active region array formed in the second well region; a second power region formed in the second well region, the second active region array and the second power region being separate from each other in the first direction; and a first dummy active region formed in the first well region between the first active region and the first power region, the first dummy active region being separate from the first active region and the first power region in the first direction.

Semiconductor device

A semiconductor package having a structure in which a decoupling capacitor is disposed to be adjacent with a semiconductor chip using a vertical chip interconnection (VCI) to improve power integrity. The semiconductor package includes a semiconductor substrate including a first finger pad and a second finger pad, a semiconductor chip mounted on the semiconductor substrate and including a first chip pad and a second chip pad, a bonding tape electrically connecting the first finger pad and the first chip pad, and a bonding wire electrically connecting the second finger pad and the second chip pad. Here, the bonding tape is formed to make contact with a sidewall of the semiconductor chip in a vertical direction of the semiconductor chip.

Semiconductor package with sidewall contacting bonding tape

A beamforming method is provided. The beamforming method includes determining different beams for pieces of user equipment based on channel information fed back from the pieces of user equipment, predicting beam qualities of the pieces of user equipment for the beams, determining whether the beam qualities satisfy Quality of Service (QoS) for the pieces of user equipment, generating a wide nulling beam by applying wide nulling to a second beam having a side lobe acting as interference against one first beam, when the beam quality of the first beam does not satisfy the QoS; predicting beam qualities for the beams including the wide nulling beam instead of the second beam, and simultaneously communicating with the user equipment through the beams including the wide nulling beam instead of the second beam, when the beam qualities for the beams including the wide nulling beam instead of the second beam satisfy the QoS.

Beamforming method and apparatus for serving multiple users

Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module substrate provided with a plurality of signal wires on an upper surface thereof, a package substrate disposed on the module substrate, a semiconductor chip disposed on one surface of the package substrate, and a plurality of external connection terminals disposed on another surface of the package substrate.

Semiconductor package, module substrate and semiconductor package module having the same

Provided is a semiconductor package including a semiconductor chip having one surface on which chip pads are formed, and a redistribution structure formed on the one surface of the semiconductor chip. The redistribution structure includes a redistribution layer connected to the chip pads and a redistribution insulating layer interposed between the semiconductor chip and the redistribution layer. The redistribution insulating layer includes a first insulating portion having a first dielectric constant and a second insulating portion having a second dielectric constant that is different from the first dielectric constant. The first insulating portion and the second insulating portion are connected to each other in a horizontal direction.

A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.

Stacked package structure and method of forming a package-on-package device including an electromagnetic shielding layer

A semiconductor device, a semiconductor package, and an electronic device are provided. The electronic device includes a first semiconductor package disposed on a circuit substrate. A second semiconductor package is provided on the circuit substrate and spaced apart from the first semiconductor package. An insulating electromagnetic shielding structure is provided on the top and the lateral surfaces of the first semiconductor package. A conductive electromagnetic shielding structure is provided on the circuit substrate to cover the first and second semiconductor packages and the insulating electromagnetic shielding structure.

Semiconductor device, semiconductor package, and electronic device

A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Semiconductor chip and a semiconductor package having a package on package (POP) structure including the semiconductor chip

A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Semiconductor device including coupling conductive pattern

Growing community of inventors

Suwon-si, South Korea

Yong-hoon Kim