Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft Kabushiki Kaisha Toshiba

Yohji Watanabe

Daisuke Kato

Munehiro Yoshida

Ryo Fukuda

Kenji Tsuchida

Tohru Furuyama

Takashi Taira

Kenji Ishizuka

Takashi Yamada

Koji Sakui

Takashi Ohsawa

Masaki Kondo

Fumiyoshi Matsuoka

Eiichi Makino

Hiroshi Ikeda

Mitsutoshi Nakamura

Shuso Fujii

Peter Poechmueller

A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.

Semiconductor memory device

A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.

Semiconductor integrated circuit device

A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.

Semiconductor device

A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.

A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.

Semiconductor storage device formed to optimize test technique and redundancy technology

There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair regions as a group of first/second normal elements with permission of replacement by each first/second redundant element.

A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.

Semiconductor memory device having redundancy system

The present invention includes a cost efficient method of substantially increasing the data bandwidth of a dynamic random access memory (DRAM) device initially configured to operate in an extended data output (EDO) mode, the EDO DRAM device including at least one storage cell, a column decoder, an internal read/write data bus and an off chip driver latch, the column decoder decoding a column address upon receipt thereof such that data stored in the at least one storage cell corresponding to the decoded column addresses is placed on the internal read/write data bus in response to the receipt of an address transition detection (ATD) pulse generated by the dynamic memory device and further wherein output data is stored in the off chip driver latch in response to a transfer pulse. The method includes the steps of temporarily suppressing the generation of the ATD pulse such that data selected from the at least one storage cell is not placed on internal read/write data bus until after a delayed generation of the ATD pulse in response to the falling edge of a column address strobe (CAS) signal, such that a first pipeline stage is thereby substantially defined.

Methods and apparatus for increasing data bandwidth in a dynamic memory device by generating a delayed address transition detection signal in response to a column address strobe signal

A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair region as group of first/second normal elements with permission of replacement by each first/second redundant element.

A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.

Semiconductor integrated circuit device having fuses and fuse latch circuits

In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.

Semiconductor memory device of shared sense amplifier system

A data input/output buffer is connected between first data lines and second data lines. An equalizing circuit and a data latch circuit are connected to the second data lines. The equalizing circuit maintains the second data lines in reset condition, during normal operation. It temporarily releases the second data lines from the reset condition, in response to an output from an address-transition detecting circuit, thereby to transfer the data from the data input/output buffer. The data latch circuit latches the data transferred to the second data lines, in response to the output from the address-transition detecting circuit.

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Yokohama, Japan

Yohji Watanabe