Cadence Design Systems, Inc.

Synopsys, Inc.

Versity Design, Inc.

Yogesh Goel

Ping-Sheng Tseng

Kun-Hsu K Shen

Amy Lim

Helena Krupnova

A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.

Method and system for reproducing prototyping failures in emulation

Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The logic design is simulated over a plurality of clock events. Attempts to evaluate the assertion by the evaluation engine are preformed sequentially based on input stimuli obtained from the logic design during simulation thereof. Each of the attempts results in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation.

Method and apparatus for processing assertions in assertion-based verification of a logic design

In the VCD-On-Demand system, the EDA tool has the following attributes: (1) RCC-based parallel simulation history compression and recording, (2) RCC-based parallel simulation history decompression and VCD file generation, and (3) On-demand software regeneration for a selected simulation target range without simulation rerun. When the user selects a simulation session range, the RCC System records a highly compressed version of the primary inputs from the test bench process. The user then selects a narrower region, the simulation target range, within the simulation session range for a more focused analysis. The RCC System dumps the hardware state information of the hardware model into a VCD file. The RCC System then allows the user to proceed directly to view the VCD file from the beginning of the simulation target range without having to rerun the entire simulation from the beginning of the simulation session range.

Growing community of inventors

Fremont, CA, United States of America

Yogesh Goel