United Microelectronics Corp.

Ying-Tsung Chen

Ssu-I Fu

Shih-Hung Tsai

Chien-Ting Lin

Wen-Tai Chiang

Chih-Wei Chen

Chun-Hsien Lin

Yu-Cheng Tung

Chih-Kai Hsu

Chin-Fu Lin

Yu-Hsiang Hung

Jyh-Shyang Jenq

Chi-Mao Hsu

Chao-Hung Lin

An-Chi Liu

Hsuan-Hsu Chen

Chien-Liang Lin

Ying-Chih Lin

En-Chiuan Liou

Chin-Cheng Chien

Jiunn-Hsiung Liao

Chih-Wei Yang

Wen-Han Hung

Chien-Ming Lai

Zhi-Cheng Lee

Che-Hua Hsu

Yi-Wen Chen

Chiu-Hsien Yeh

Cheng-Guo Chen

Po-Jui Liao

Shao-Wei Wang

Jie-Ning Yang

Shao-Hua Hsu

Tong-Jyun Huang

Ted Ming-Lang Guo

Guang-Yaw Hwang

Tsung-Lung Tsai

Hung-Ling Shih

Jung-Tsung Tseng

Cheng-Yu Ma

Kai-Ping Wang

A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.

Method for forming semiconductor device

A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An Oambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Oxygen treatment of replacement work-function metals in CMOS transistor gates

A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.

Semiconductor device and method of forming the same

The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Manufacturing method of non-planar FET

A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET.

Multi-gate MOSFET with embedded isolation structures

A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Semiconductor structure

A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Manufacturing method for semiconductor device having metal gate

A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Method of forming semiconductor device having metal gate

A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

Semiconductor process

Method of forming semiconductor device

Non-planar FET and manufacturing method thereof

A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

Method for manufacturing multi-gate transistor device

A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.

Semiconductor structure and method of fabricating the same

A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.

Method of forming fin structures in integrated circuits

Growing community of inventors

Kaohsiung, Taiwan

Ying-Tsung Chen