Advanced Micro Devices Corporation

Ying Shiau

Yung-Tao Lin

Zhi-Min Ling

James Minsu Pak

Yeng-Kaung Peng

Siu-May Ho

Susan H Chen

Ming Chun Chen

Tho Le La

Chern-Jiann Lee

Richard Charles Kittler

Mikkel Lantz

Jerry Tsiang

Thao H Vo

Wanyee Apple Chow

An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

Apparatus for detecting defect sizes in polysilicon and source-drain

Method for detecting defect sizes in polysilicon and source-drain

An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.

Arrangement and method for detecting sequential processing effects in

An apparatus and method for selecting products to inspect for defects performs in-situ monitoring of a processing tool during a manufacturing processing step. The data from the in-situ monitoring for a test run of products is correlated by a neural network with data collected during inspection of the test products for defects. During a production run of products, the in-situ monitor data is provided to the neural network which, based on the input data and the correlation, predicts the values of the data that would be collected upon inspection of the products. Specific products from the production run are selected for inspection based upon the predicted values.

Method and apparatus for inspecting manufactured products for defects in

An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively suicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

Methods and apparatus are disclosed for testing integrated circuits at the wafer level and for integrating test results, calculation of lifetimes and generation of trend charts in a common database following testing. A wafer tester controller is supplemented with additional hardware and software to avoid data transfer errors and facilitate processing and storage of test results. The data base is available over a network to all areas of an organization.

Method and apparatus for automated wafer level testing and reliability

An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers. The report is also stored in a pattern database to serve as a library for future reference of previously recognized fault patterns, thereby to bypass the need to perform a failure analysis for matching fault patterns.

Method and apparatus for pattern recognition of wafer test bins

An arrangement and method for detecting sequential processing effects on devices to be manufactured in a manufacturing process extracts data regarding responses of the devices to a process step in the manufacturing process and data regarding a processing sequence of the devices in that process step. The extracted data is refined before analysis and control chart rules are then applied to the refined data. These control chart rules detect whether there are any unusual processing effects caused by the sequence of processing of the devices in any one of the individual processing steps. Application of control chart rules to the refined data allows an automatic determination of whether there are any rule violations. One or more control charts which have a rule violation are automatically generated when it is determined that there is a rule violation. Process engineers may then use the automatically generated charts to direct their efforts at improving the manufacturing process.

An automated wafer defect management system in which wafer defect data are collected from wafer inspection instruments, converted into a standard data format and made available through a central database system to workstations for review, analysis, and evaluation.

Defect management system for productivity and yield improvement

In a final wafer sort (FWS) testing facility, the raw log-out data that is output by FWS test stations is augmented with additional differentiating data to thereby produce differentiable log-outs that can be sorted according to a variety of criteria including: product number or product family, time of test, specific wafer, specific production lot, intra-reticle site number, machine operator, and the specific swappable units of equipment that participated in the FWS testing. The differentiable log-outs are stored in a database and are periodically accessed by an automatic watchdog system that tests for exception conditions calling for immediate or long-term response. Corresponding alarm signals and trend reports are automatically generated and distributed to responsible personnel and/or reactive machine-systems as appropriate. The alarm distribution mechanism includes automatic paging of personnel by wireless beeper and/or e-mail. Immediate response alarms include exception conditions detected for accumulated bin counts on a per-wafer or per-lot basis. Long term alert reports include those that detect increased error rates and possible wear down of replaceable probe cards.

Watchdog system having data differentiating means for use in monitoring

Structures to extract defect size information of poly and source-drain

A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the layers or a defect sensitive area index for each of the layers using the first and second information. The yield management station also determines a priority for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the layers.

Growing community of inventors

San Jose, CA, United States of America

Ying Shiau