Taiwan Semiconductor Manufacturing Comp. Ltd.

Ying-Liang Chuang

Ming-Hsi Yeh

Kuo-Bin Huang

Ming-Chi Huang

Ju-Li Huang

Yu-Chi Pan

Chun-Sheng Liang

Hsin-Che Chiang

Yao-Wen Hsu

Chun-Cheng Chou

Liang-Guang Chen

Chun-Neng Lin

Chi-Jen Liu

Li-Chieh Wu

Shich-Chang Suen

Ming-Liang Yen

Chun-Ming Yang

Kuo Bin Huang

Chun-Chih Cheng

Kuan-Wei Lin

Chih-Long Chiang

Yu-Te Su

Yen-Ming Chen

Li-Zhen Yu

Dian-Hau Chen

Chien-Hao Chen

Hsiang-Ku Shen

Chih-Tang Peng

Jr-Hung Li

Kuo-Ju Chen

Chi-On Chui

De-Wei Yu

Shih-Wei Wang

Bo-Cyuan Lu

Tsung-Chieh Hsiao

Hung-Yi Huang

Min-Hsiu Hung

Yen-Chun Huang

Cheng-Po Chau

Chia-Lin Chuang

Jin-Mu Yin

Chia-Ling Chung

Yu-Fang Huang

Li-Chen Lee

Ren-Kai Chen

Cheng-Chieh Tu

Tefu Yeh

Hao-Hsin Chen

Pei Yun Chung

Disclosed is a method of forming gate structures for n-type and p-type transistors. The method includes: forming an interfacial layer and high-K (HK) dielectric layer for the gate structures; forming an n-type metal layer over the HK dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the HK dielectric layer by fluorine passivation; patterning photo resist (PR) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned PR material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.

Metal gate patterning

A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.

Method for modifying metal-including material in semiconductor manufacturing process

A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.

Fin field-effect transistor and method of forming the same

The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

Gate resistance improvement and method thereof

A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

Semiconductor devices and method of forming the same

Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

Semiconductor device and method of manufacture

A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.

A method for selectively removing a tungsten-including layer includes: forming a tungsten-including layer which has a first portion and a second portion; performing a treatment on a surface region of the first portion of the tungsten-including layer so as to convert tungsten in the surface region into tungsten oxide; and partially removing the tungsten-including layer using an etchant which has a higher etching selectivity to tungsten than tungsten oxide such that the second portion of the tungsten-including layer is fully removed, and the first portion of the tungsten-including layer, having the tungsten oxide in the surface region, is at least partially retained.

Method for partially removing tungsten in semiconductor manufacturing process

Fin Field-Effect transistor and method of forming the same

Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

Metal gate using monolayers

A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.

Passivation layer for protecting semiconductor structures

A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.

Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

Self-protective layer formed on high-K dielectric layer

A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

Etch method for interconnect structure

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Zhubei, Taiwan

Ying-Liang Chuang