Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

National Taiwan University

Ying-Ching Shih

Szu-Wei Lu

Chih-Wei Wu

Jing-Cheng Lin

Chen-Hua Douglas Yu

Pu Wang

Li-Chung Kuo

Shang-Yun Hou

Kuan-Yu Huang

Hsien-Ju Tsou

Shin-Puu Jeng

Chi-Hsi Wu

Long Hua Lee

Wen-Chih Chiou

Hsien-Pin Hu

Wen-Hsin Wei

Sung-Hui Huang

Tsung-Fu Tsai

Szu Wei Lu

Kung-Chen Yeh

Po-Hao Tsai

Jiun-Ting Chen

Jung-Hua Chang

Yu-Wei Chen

Cheng-Chieh Li

Chin-Fu Kao

Shu-Hang Liao

I-Ting Chen

Cheng-Lin Huang

Cheng-Chieh Hsieh

Weng-Jin Wu

Hsing-Kuo Hsia

Kuo-Ching Hsu

Heh-Chang Huang

Yushun Lin

Chih-Chieh Hung

Ming-Fa Chen

Chen-Shien Chen

Der-Chyang Yeh

An-Jhih Su

Kuo-Chung Yee

Shu-Ming Chang

Yu-Hung Lin

Yu-Hua Chen

Sao-Ling Chiu

Ming-Shih Yeh

Ping-Kang Huang

Ting-Yu Yeh

Wen-Wei Shen

Chen-Hsuan Tsai

Ying-Da Wang

Chia-Nan Yuan

Pai Yuan Li

Chih-Ta Shen

Li-Hui Cheng

Kuo-Chiang Ting

Cheng-Ta Ko

Shih-Ting Lin

Weiming Chris Chen

Enboa Wu

Yuan-Chang Lee

Long-Hua Lee

Jeh-Yin Chang

Yi Chou

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Package structure and method of fabricating the same

A method of forming a semiconductor package includes: forming a first package component including a first and a second conductive bumps; forming a second package component including a third and a fourth conductive bumps, where dimensions of the first and second conductive bumps are less than dimensions of the third and fourth conductive bumps; and forming a first and a second joint structures to bond the second package component to the first package component. A first angle between an exposed sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the sidewall of the first conductive bump is less than a second angle between an exposed sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the sidewall of the second conductive bump.

Joint structure in semiconductor package and manufacturing method thereof

A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.

Package structure including stacked pillar portions and method for fabricating the same

A package assembly may include a package substrate, a package lid attached to the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot extending from the plate portion inside the outer foot, and an adhesive that adheres the outer foot to the package substrate and the inner foot to the package substrate.

Package assembly including a package lid having an inner foot and methods of making the same

A package structure including a semiconductor die, a redistribution circuit structure, a backside dielectric layer, conductive terminals, an electronic device, and an underfill is provided. The semiconductor die laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes redistribution conductive layers and thermal enhancement structures electrically insulated from the redistribution conductive layers, and the thermal enhancement structures are thermally coupled to the semiconductor die. The backside dielectric layer is disposed on the redistribution circuit structure. The conductive terminals penetrate through the backside dielectric layer. The electronic device is disposed over the backside dielectric layer and electrically connected to the redistribution circuit structure through the conductive terminals. The underfill is disposed between the backside dielectric layer and the electronic device, wherein the underfill is thermally coupled to the thermal enhancement structures.

Package structure

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Semiconductor package and manufacturing method thereof

A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant. The top metal layers, the bottom metal layers, and the intermetallic layers are in contact with the first encapsulant.

A package structure including a first semiconductor die, a second semiconductor die, a molding compound, a bridge structure, through insulator vias, an insulating encapsulant, conductive bumps, a redistribution layer and seed layers is provided. The molding compound encapsulates the first and second semiconductor die. The bridge structure is disposed on the molding compound and electrically connects the first semiconductor die with the second semiconductor die. The insulating encapsulant encapsulates the bridge structure and the through insulator vias. The conductive bumps are electrically connecting the first and second semiconductor dies to the bridge structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the bridge structure. The seed layers are respectively disposed in between the through insulator vias and the redistribution layer.

Package structure having bridge structure for connection between semiconductor dies

A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Method of forming integrated fan-out packages with built-in heat sink

A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies.

Shift control method in manufacture of semiconductor device

A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Underfill structure for semiconductor packages and methods of forming the same

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.

Chip package structure

Growing community of inventors

Hsinchu, Taiwan

Ying-Ching Shih