Integrated Device Technology, Inc.

Alpha Omega Semiconductor Inc.

Alpha and Omage Semiconductor Inc.

Yiming Gu

Hong Chang

Yeeheng Lee

Wenjun Li

Hongyong Xue

Paul Thorup

Yang Xiang

John L Sturtevant

Hamza Yilmaz

Madhur Bobde

Lingpeng Guan

Terence Huang

Sekar Ramamoorthy

Jowei Dun

Guo-Qiang Lo

Lingbing Chen

Chih-Hsiang Chen

Dyiann Chou

Chantha Lom

Anging Zhang

Boxiu Cai

Winston Wu

This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Power device with high aspect ratio trench contacts and submicron pitches between trenches

A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Split-gate trench power mosfet with protected shield oxide

Split-gate trench power MOSFET with protected shield oxide

A method of monitoring an epitaxial growth geometry shift is disclosed. First, second and third trenches are formed on a semiconductor wafer. An epitaxial layer is grown. The epitaxial layer covers the first trenches and the second trenches but not the third trenches. First and second recesses on a top surface of the epitaxial layer are formed. First and second openings aligned with the first and the second recesses and a third openings aligned with the third trenches are formed in a photoresist layer. A corresponding first offset between a top center and a bottom center of each first recess is measured. An offset value of the top center from the bottom center of said each first recess is determined. A corresponding second offset between a top center of each second recess and a center of corresponding second opening is determined. A corresponding third offset between a center of each third trench and a center of corresponding third opening is measured. A corresponding offset value of each second recess from the difference between corresponding second offset and corresponding third offset is determined.

Method for monitoring epitaxial growth geometry shift

This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.

Recycle photochemical to reduce cost of material and environmental impact

Methods for determining tolerances are disclosed that can be used for determining whether a lot of semiconductor wafers needs to be reworked. Overlay tolerance, critical dimension tolerance and a dynamic line edge placement tolerance are determined using error measurements that are taken from sample wafers in the lot, giving tolerances that reflect the error state of that particular lot of semiconductor wafers.

Dynamically coupled metrology and lithography

A method for determining photoresist thickness is disclosed that can be used in a semiconductor fabrication process. A layer of material is formed that has one or more common characteristic relative to the material in the layer that is to be patterned in the semiconductor fabrication process. A layer of photoresist is then formed that has varying thickness. The thickness of the layer of photoresist is determined at a plurality of different points. The layer of photoresist is exposed, developed and etched. The remaining structures are then analyzed to determine photoresist thickness to be used in the semiconductor fabrication process. The determined photoresist thickness is then used in the semiconductor fabrication process to form structures on a semiconductor wafer.

Method for determining photoresist thickness and structure formed using determined photoresist thickness

The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate, and an etch is performed so as to form trenches within the semiconductor substrate. An anti-reflective film is deposited such that it extends within the trench. A dielectric film is deposited over the anti-reflective film such that it fills the trench. A heating process step is then performed to anneal the substrate, rounding the corners of the trench. A chemical mechanical polishing process is performed to remove those portions of the anti-reflective film and the dielectric film that overlie the hard mask. The hard mask is then removed, producing a shallow trench isolation structure that prevents lifting and notching in subsequent fabrication steps.

Method for forming shallow trench isolation structure with anti-reflective liner

A method for generating a photoresist structure is disclosed in which a layer of photoresist is deposited over a semiconductor substrate. In a first exposure, the layer of photoresist is exposed to deep ultraviolet light. A second exposure is then performed using a different wavelength of light to pattern the layer of photoresist. The photoresist is then developed so as to form a photoresist structure having reduced thickness and rounded corners. This gives a photoresist structure having a reduced shadow area. An angled ion implant can then be performed using the photoresist structure as a mask.

Dual-wavelength exposure for reduction of implant shadowing

A method for forming a photoresist structure that does not have swelling defects. A layer of low activation energy deep ultraviolet photoresist is disposed over a layer that is to be patterned. A layer of high activation energy deep ultraviolet photoresist is then deposited such that the layer of high activation energy photoresist directly overlies the layer of low activation energy photoresist. The two photoresist layers are then processed by performing exposure, post-exposure bake, and development steps to form a photoresist structure. An etch step is then performed so as to form a patterned layer that does not have swelling defects.

Dual-layer deep ultraviolet photoresist process and structure

A method for generating a swing curve and a photoresist feature formed using the swing curve. A layer of photoresist is formed that has varying thickness. The thickness of the layer of photoresist is determined at a plurality of points. The semiconductor wafer is then exposed and developed to form a photoresist structure that includes features. For each of the points at which thickness was determined, the size of a corresponding feature is determined. A curve is then determined that correlates the thickness measurements and the size measurements. The resulting swing curve is then used to determine a thickness for photoresist deposition and a photoresist layer is deposited, exposed, and developed to obtain a photoresist feature having the desired size.

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Hillsboro, OR, United States of America

Yiming Gu