Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Yii-Chian Lu

Fang-Mei Chao

Lee-Chung Lu

Po-Hsiang Huang

Fong-yuan Chang

Keh-Jeng Chang

Yu-Hao Chen

Jyh Chwen Frank Lee

Chih-Nan Cheng

Shin-Puu Jeng

Chine-Gie Lou

Jyh-Nan Cheng

A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

Heat dissipation in semiconductor packages and methods of forming same

An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An Nsource doping region, which functions as a source of the NMOS device, is disposed in the P-well. An Ndrain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.

Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof

The invention provides an ESD protection structure, compatible with the bipolar-CMOS-DMOS (BCD) processes, which provides an enhanced protection performance and better heat dissipation performance. The design of the ESD structures in present invention takes advantage of bipolar punch characteristics of the parasitic bipolar structure to bypass the ESD current, thus significantly reducing the trigger voltage and increasing the ESD protection level. In addition, the ESD protection circuit of the present invention can improve heat dissipation by avoid current crowding near the surface.

Electrostatic discharge protection structure

A method for forming a bottom storage node of a capacitor for a DRAM memory cell on a substrate is disclosed. The method comprises the steps of: forming a first oxide layer onto the substrate; forming a conductive contact plug in the first oxide layer, the contact plug extending down to the substrate; forming a second oxide layer over the first oxide layer and the contact plug; forming a silicon nitride layer over the second oxide layer; patterning and etching the silicon nitride layer and the second oxide layer to form a trench over the contact plug; forming a layer of rugged insitu doped polysilicon layer over the silicon nitride layer and along the walls and bottom of the trench; depositing a photoresist layer over the rugged insitu doped polysilicon layer and filling the trench; performing a first reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is reached; performing a second reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is removed, the second reactive ion etching step formulated to remove the rugged insitu doped polysilicon layer faster than the photoresist layer; and performing a chemical dry etching step to smooth out the sharp corners of the rugged polysilicon layer.

Method for forming a crown capacitor

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Taipei, Taiwan

Yii-Chian Lu