Chartered Semiconductor Manufacturing Ltd (corporation)

Stmicroelectronics Gmbh

Yih-Shung Lin

Charles Lin

Erzhuang Liu

Jia Zhen Zheng

Wei Lu

Alex Kalnitsky

Marvin De-Dui Liao

Kho Liep Chok

Liu Erzhuang

Xiaosong Tang

Erzhuang Lzu

A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Enhanced planarization technique for an integrated circuit

A method for forming a barrier layer upon an electrode contact. There is first provided a silicon substrate layer having an electrode contact region formed within the silicon substrate layer. There is then formed over the silicon substrate layer a titanium layer, where the titanium layer contacts the electrode contact region of the silicon substrate layer. There is then processed thermally the titanium layer in a nitrogen containing atmosphere to form a titanium silicide layer in contact with the electrode contact region and a titanium nitride layer formed thereover, where the titanium layer is completely consumed in forming the titanium silicide layer and the titanium nitride layer. Finally, there is formed upon the titanium nitride layer a barrier layer.

Titanium nitride/titanium tungsten alloy composite barrier layer for integrated circuits

A wafer chuck for positioning and releasably holding a wafer includes a support platform having an upper surface for positioning and supporting the wafer. Wafer banking pins are affixed to the support platform for positioning the wafer. A lift device acting on the wafer when it rests on the support platform to move the wafer relative to the support platform in a slanted direction away from the support platform and wafer banking pins. The lift device has a plurality of wafer lifting fingers that cooperatively extend in a biased and substantially vertical direction are disposed in a pattern to be supportive of the wafer. Each of the wafer lifting fingers has an end portion that is movable relative to the support platform between a first position at which it is retracted from the upper surface of the support platform and a second position at which it protrudes from the upper surface of the support platform so as to engage the wafer to lift it relative to the support platform.

Self aligning wafer chuck design for wafer processing tools

A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a polysilicon resistor. There is then formed over the polysilicon resistor a first dielectric layer formed of a silicon nitride dielectric material deposited employing a plasma enhanced chemical vapor deposition (PECVD) method other than a high density plasma chemical vapor deposition (HDP-CVD) method. Finally, there is then formed over the first dielectric layer a second dielectric layer deposited employing a high density plasma chemical vapor deposition (HDP-CVD) method, where first dielectric layer attenuates a decrease in resistance of the polysilicon resistor incident to forming the second dielectric layer over the first dielectric layer.

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride barrier

A method for fabricating a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed horizontally spaced over the substrate a plurality of patterned microelectronics structures. There is then formed over the substrate and the plurality of patterned microelectronics structures a microelectronics layer. The microelectronics layer has a first region of the microelectronics layer interposed between the plurality of patterned microelectronics structures and a second region of the microelectronics layer not interposed between the plurality of microelectronics structures. Finally, there is processed through a grazing angle method the microelectronics layer, where the grazing angle method processes substantially all of the second region of the microelectronics layer without substantially processing the first region of the microelectronics layer. There is also disclosed a apparatus through which may be practiced the grazing angle method, where the apparatus employs a charged particle beam within the grazing angle method and where the charged particle beam is spirally magnetically constrained by a magnetic field perpendicular to the substrate.

Grazing incident angle processing method for microelectronics layer

A method of forming a portion of a semiconductor integrated circuit having a semiconductor substrate as well as the resulting integrated circuit. In the inventive method, various steps are involved. In one embodiment, for example, the method steps are as follows. First, there is formed a first polysilicon layer overlying and in contact with the semiconductor substrate. Second, a plurality of conductive structures are patterned from the first polysilicon layer. Third, there is formed a dielectric layer having an upper planar surface and having a lower surface contacting the semiconductor substrate and the plurality of conductive structures from the first polysilicon layer. Fourth, there is formed a second polysilicon layer overlying and in contact with the dielectric layer. Fifth, a plurality of conductive structures are formed from the second polysilicon layer. Lastly, there is formed a metallic layer over the plurality of conductive structures from the second polysilicon layer.

Integrated circuit with planarized dielectric layer between successive

A method is described for filling narrow gaps in a surface that is being overcoated. This has been achieved by heating the overcoating layer to a sufficient extent so that it flows relatively easily. This, in combination with externally applied pressure, causes the overcoating layer to effectively fill any narrow gaps in the surface being coated. Temperature and pressure are applied for a time that is sufficient to allow small quantities of gas that may have become trapped in the gaps to bubble to the surface. In an alternative embodiment, the surface to be coated is subjected to negative pressure prior to application of the coating. This eliminates the possibility of trapping gas in the gaps so a waiting time is no longer necessary.

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Singapore, Singapore

Yih-Shung Lin