Macronix International Co., Ltd.

Yih-Shan Yang

Chun-Hsiung Hung

Meng-Fan Chang

Shin-Jang Shen

Shou-Nan Hung

Yao-Jen Kuo

Ya-Jui Lee

Che-Ping Chen

Wei-Han Chen

A memory device and a detection method for detecting a defeated status of a memory cell are provided. The memory device is, for example a three dimensional NAND flash memory circuit, and provides a storage media with high-performance and high-capacity. The detection method includes: searching status data stored in a page buffer, finding set status memory cells, and acquiring set status data; storing status data in a storage device; setting one of latches in the page buffer as a selected latch after a first half of the levels of the programming operation have been completed; storing each setting data in the selected latch; and check each set status memory cell according to the each set status data to determine whether the set status memory cell is maintained in the set status.

Memory device and detection method for defeated status of memory cell

A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.

Push-pull output driver and operational amplifier using same

An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a first circuit to generate a temperature-dependent voltage (TDV) that is dependent on an operating temperature of the integrated circuit, and a second circuit to generate a plurality of temperature reference voltages, based on or more codes. One or more comparator circuits compare individual ones of the plurality of reference voltages with the TDV, to generate one or more comparison signals that are indicative of the operating temperature of the integrated circuit.

Piecewise linear and trimmable temperature sensor

A flash memory and an operation method thereof are provided. The flash memory includes a plurality of memory cell strings and a pass voltage generator. Each of the memory cell strings includes a plurality of memory cells. The pass voltage generator is configured to provide a pass voltage to a plurality of word lines of a plurality of unselected memory cells of a selected memory string. During a reading operation, the pass voltage generator raises the pass voltage from a first voltage at a first time point, and raises the pass voltage to a second voltage at a second time point. The second voltage is lower than a target voltage times a preset ratio The first time point is earlier than a start time point of a bit line voltage received by the selected memory cell, and the second time point occurs at the start time point of the bit line voltage.

Flash memory and operation method thereof for controlling raising speed of the read pass voltage

A voltage subtracter includes a first charge storage device and a second charge storage device. The first charge storage device receives a first voltage and a second voltage during a first time period, and storages a first difference voltage between the first voltage and the second voltage. The second charge storage device receives a reference ground voltage and the first voltage during a second time period, and storages a second difference voltage between the reference ground voltage and the first voltage. The first charge storage device and the second charge storage device are coupled to an output end during a second time period, and a charge sharing operation is operatedon the first charge storage device and the second charge storage device to generate an output voltage on the output end.

Voltage subtracter and operation method for subtracting voltages

A low dropout (LDO) regulating device includes a regulator and a pre-charger. The regulator is configured to adjust an output voltage provided to an output node in accordance with a voltage difference between a first reference voltage and a feedback voltage on a feedback node, wherein the feedback node is coupled to the output node. The pre-charger is electrically connected to the regulator, and is electrically connected to the feedback node for charge sharing.

Low dropout regulating device and operating method thereof

A memory device comprises a first NAND string that includes a first plurality of memory cells and a first string select switch arranged in series, the first string select switch disposed between a first bit line and a first end of the first plurality, a second NAND string that includes a second plurality of memory cells and a second string select switch arranged in series, the second string select switch disposed between a second bit line and a first end of the second plurality, word lines coupled to memory cells in the first plurality and memory cells in the second plurality, and a string select line coupled to the first and second string select switches. A method of operating such a memory device comprises applying a voltage varying in a manner complementary to absolute temperature to at least one of the word lines and the string select line.

Temperature compensation for unselected memory cells and string select switches in NAND flash memory

Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.

Method and apparatus for determining status element total with sequentially coupled counting status circuits

A semiconductor device includes an amplifier, a pass transistor, a compensation circuit, and a bias voltage generator. The amplifier has an output terminal. The pass transistor has a gate and an output terminal. The gate is coupled to the output terminal of the amplifier, and the output terminal of the pass transistor is coupled to a load. The compensation circuit is coupled between the output terminal of the amplifier and the output terminal of the pass transistor. The compensation circuit has a variable impedance. The bias voltage generator is coupled between the output terminal of the pass transistor and the compensation circuit.

Semiconductor device having output compensation

An N bit digital-to-analog converter DAC is based on a first stage including a first set of resistors corresponding to higher order bits of the digital input, and a second stage including a second set of resistors corresponding to lower order bits of the digital input. A plurality of pass transistors is arrange to connect a first subset of the first set of resistors in the first stage selected in response to a digital input to a second subset of the second set of resistors in the second stage selected in response to the digital input. A means for reducing variations in a sum of on-resistances Rof the pass transistors in the plurality of pass transistors selected in response to a digital input is provided, resulting in more uniform steps in output voltage of the DAC over a wider range.

Two stage digital-to-analog converter

A circuit includes a detection node and a feedback node adapted to communicate with a reference circuit. A clamping transistor includes current conducting terminals and a gate coupled to the detection node. An amplifier transistor includes current conducting terminals in series with the current conducting terminals of the clamping transistor and a gate coupled to the detection node. The amplifier transistor is configured to cause a second voltage to be provided to the feedback node in response to the clamping transistor receiving a first voltage from the detection node.

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Hsinchu, Taiwan

Yih-Shan Yang