Taiwan Semiconductor Manufacturing Comp. Ltd.

Yih-Ann Lin

Ryan Chia-Jen Chen

Chao-Cheng Chen

Jr Jung Lin

Kuo-Tai Huang

Chia Tai Lin

Yu Chao Lin

Yi-Shien Mor

Ming-Ching Chang

De-Fang Chen

Chien-Hao Chen

Chun-Hung Lee

Tzu-Yen Hsieh

Yi-Hsing Chen

An-Shen Chang

Chii-Horng Li

Yen-Ru Lee

Chih-Chang Hung

Chih-Shan Chen

Tzu-Ching Lin

Donald Y Chao

Chieh-Ning Feng

Roger Tai

Yen-Ming Chen

Feng-Cheng Yang

Kai-Hsuan Lee

Yu-Chao Lin

Bo-Yu Lai

An Chyi Wei

Chen-Huang Huang

Ming-Jhe Sie

Ryan Chia-jen Chen

Chun-Liang Lai

Chih-Han Lin

Sai-Hooi Yeong

Jr-Jung Lin

Sheng-Liang Pan

Kuo-Liang Lu

Li-Wei Yin

Tzu-Wen Pan

Jih-Sheng Yang

Ryan Chen

Chang Ming-Ching

Shih-Chieh Chao

Syun-Ming Jang Jang

Hun-Jan Tao

Ming-Hsi Yeh

Chi-Hung Liao

Weng Chang

Chia-Wei Chang

Yu-Hsien Lin

Kai-Ming Ching

Hao-Ming Lien

Cheng-Yu Chu

Chun-Li Chou

Bing-Hung Chen

Bi-Ming Yen

Yi-Chen Huang

Sai-hooi Yeong

Chia Ming Liang

Jih-Jse Lin

Tung-Heng Shie

Yu Hsi Wang

Joseph Lin

Weng Cheng

A method includes forming a gate stack for a short-channel device and a longer-channel device; forming a first metal cap layer over the gate stacks for the short-channel device and the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess; forming a first dielectric cap layer in the metal-cap recess; selectively removing in parallel, a portion of the gate stacks and first metal cap layer for the short-channel device and the longer-channel device; forming a first channel recess between spacers in the short-channel device and a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device by the selectively removing; wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nm.

Semiconductor device and manufacturing method thereof

Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Tunable structure profile

A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Method of making a FinFET device including a step of removing a portion of a fin

A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

Air spacers around contact plugs and method forming same

In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Self-aligned contact air gap formation

A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

Fin field-effect transistor devices and methods of forming the same

A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Methods for forming fin field-effect transistors

A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Method of forming an integrated circuit using a patterned mask layer

A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.

Gate stacks for semiconductor devices of different conductivity types

Method of making a FinFET device including a step of recessing a subset of the fins

Growing community of inventors

Jhudong, Taiwan

Yih-Ann Lin