Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Semiconductor Manufacturing International Corp.

Yibin Huang

Wanjuan Zhang

Fan Zhang

Yao Xu

Feng Bai

Winnie Liu

Embodiments and implementations of the present disclosure provide assistant pattern configuration methods, masks and forming methods thereof, and related devices. One form of a configuration method includes: providing a main pattern having an edge extending along a first direction, where a second direction is perpendicular to the first direction, the main pattern having a first optimal focal plane in the first direction and a second optimal focal plane in the second direction when exposed, and where there is an optimal focal plane offset between the first optimal focal plane and the second optimal focal plane; providing an initial assistant pattern around the main pattern; extracting a configuration parameter of the initial assistant pattern, the configuration parameter corresponding to the optimal focal plane offset; obtaining configuration information corresponding to a preset optimal focal plane offset based on an adjustment of the configuration parameter; and configuring an assistant pattern around the main pattern according to the configuration information. Embodiments and implementations of the present disclosure can improve lithographic quality.

Assistant pattern configuration method, mask and forming method thereof, and related device

An alignment method includes dividing a wafer into a plurality of regions including a first region and a second region, and each region contains a plurality chip areas. The method also includes obtaining alignment offset values for the first region, and determining a first alignment compensation equation for the first region. The method also includes obtaining alignment offset values for the second region, and determining a second alignment compensation equation for the second region. Further, the method includes determining whether a chip area to be exposed is in the first region or the second region, when the chip area is in the first region, using the first alignment compensation equation to adjust alignment of the wafer and, when the chip area is in the second region, using the second alignment compensation equation to adjust the alignment of the wafer.

Mask pattern alignment method and system

A method of testing a scattering bar by simulation includes preparing an OPC mask model including a main pattern and a scattering bar pattern, forming a scattering bar OPC model by adjusting an image plane of the OPC mask model located at a middle portion of a photoresist layer to a top portion of the photoresist layer, simulating an exposure of the scattering bar OPC model, simulating a profile of the exposed scattering bar OPC model, and testing the simulated profile.

Method of detecting a scattering bar by simulation

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Shanghai, China

Yibin Huang