Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfounders Singapore Pte. Ltd.

Yiang Aun Nga

Ming Zhu

Pinghui Li

Eng Huat Toh

Danny Pak-Chum Shum

Kheng Chok Tee

Zhao Lun

Wang Ling Goh

Diing Shenp Ang

Shi Ya Phyllis Lim

Su Yi Susan Yeow

Yeen Tat Chan

Wanbing Yi

Darin A Chan

Fan Zhang

Shunqiang Gong

Danny PakChum Shum

Shu Zhong

Weining Cheng

Disclosed are a system and method for automatically and systematically generating device-based design rules and corresponding device-based design rule checking (DRC) codes. In the system and method, design rules associated with specific devices are generated based on at least one table of related data (e.g., maturity status information, restriction status information, etc.) for different devices. Based on the design rules and on unique definitions for the specific devices, design rule checking (DRC) codes associated with the specific devices are generated. By using this approach, comprehensive and accurate device-based design rules and corresponding device-based DRC codes can be quickly generated to ensure acceptable product reliability and yield. Furthermore, processes used to generate the device-based DRC codes can be iteratively repeated (e.g., when the information used for generating the unique definitions of devices and/or generating the design rules changes) to update the device-based DRC codes and, thereby ensure DRC accuracy.

System and method for automatic generation of device-based design rules and corresponding design rule checking (DRC) codes

Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

Method and device for embedding flash memory and logic integration in FinFET technology

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.

Integrated circuits with memory cells and method for producing the same

LDMOS transistor structures and integrated circuits including LDMOS transistor structures are provided. An exemplary integrated circuit including an LDMOS transistor structure includes a substrate including a first region and a second region. The substrate includes a bulk layer and, in the second region, an insulator layer overlying the bulk layer and a semiconductor layer overlying the insulator layer. The integrated circuit further includes a gate structure overlying the semiconductor layer. A channel region is formed in the semiconductor layer under the gate structure. The integrated circuit also includes a well contact region on the bulk layer in the first region, a source region overlying the substrate, and a drain region overlying the substrate. A drift region is located between the drain region and the gate structure.

LDMOS transistor structures and integrated circuits including LDMOS transistor structures

A semiconductor device with embedded non-volatile memory (eNVM) is described. The device is formed on a silicon-on-insulator (SOI) substrate, such as a fully depleted SOI (FDSOI) substrate. The substrate includes a SOI region and a hybrid region. The SOI region includes the surface substrate, BOX and bulk substrate while the hybrid region includes only the bulk substrate. NVM and high voltage (HV) transistors are disposed in the hybrid region while a logic and radio frequency (RF) transistors are disposed in the SOI region. The gates of the various transistors have about coplanar top surfaces. As such, the hybrid region compensates for height differential of transistors, enabling transistors to have about coplanar top surfaces. In addition, the hybrid region enables transistors which suffer from floating body effects to be disposed therein.

Embedded non-volatile memory (NVM) on fully depleted silicon-on-insulator (FD-SOI) substrate

Integrated circuits including LDMOS transistor structures and methods for fabricating LDMOS transistor structures are provided. An exemplary method for fabricating an LDMOS transistor structure includes providing a semiconductor-on-insulator (SOI) substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer. The method includes forming a gate structure overlying the substrate. A channel region is formed in the semiconductor layer under the gate structure. The method includes forming a source region overlying the substrate. Further, the method includes forming a drain region overlying the substrate. A drift region is located between the drain region and the gate structure. Also, the method includes forming contacts to the gate structure, the source region, and the drain region.

Integrated circuits including LDMOS transistor structures and methods for fabricating LDMOS transistor structures

A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

Magnetism-controllable dummy structures in memory device

Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a first active dummy gate, a second active dummy gate, and an inactive gate overlying a substrate. The first active dummy gate is replaced with a first metal gate, where replacing the first active dummy gate includes planarizing the first metal gate, the second active dummy gate, and the inactive gate. The second active dummy gate is replaced with a second replacement metal after the first active dummy gate was replaced, where the inactive gate remains overlying the substrate.

Integrated circuits with inactive gates and methods of manufacturing the same

Devices and methods for fabricating devices with floating gates and replacement metal gates are provided. In an embodiment, a method for fabricating a device includes providing a semiconductor substrate. The method forms a floating gate and a sacrificial gate over the semiconductor substrate. Further, the method replaces the sacrificial gate with a metal gate. After replacing the sacrificial gate with the metal gate, the method forms a control gate over the floating gate.

Devices with embedded non-volatile memory and metal gates and methods for fabricating the same

Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for a fabricating a semiconductor device is provided. The method includes providing a partially fabricated semiconductor device and forming silicide regions outside of the first and second gates. The partially fabricated semiconductor device includes a semiconductor substrate, a first gate formed over the semiconductor substrate, and a second gate formed over the semiconductor substrate and spaced apart from the first gate. Silicide formation between the first gate and the second gate is inhibited.

Methods for fabricating integrated circuits and components thereof

Integrated circuits with a resistance element and gate-last techniques for forming the integrated circuits are provided. An exemplary technique includes providing a semiconductor substrate that includes a shallow trench isolation (STI) structure disposed therein. A dummy gate electrode structure is patterned overlying semiconductor material of the semiconductor substrate, and a resistor structure is patterned overlying the STI structure. The dummy gate electrode structure and the resistor structure include a dummy layer overlying a metal capping layer. A gate dielectric layer underlies the metal capping layer. An interlayer dielectric layer is formed overlying the semiconductor substrate and the STI structure. End terminal recesses for the resistance element are concurrently patterned through the dummy layer of the resistor structure along with removing the dummy layer of the dummy gate electrode structure to form a gate electrode recess. Metal gate material is deposited in the end terminal recesses and a gate electrode recess.

Integrated circuits including a resistance element and gate-last techniques for forming the integrated circuits

A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a 'T' shaped, or an 'H' shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

Growing community of inventors

Singapore, Singapore

Yiang Aun Nga