Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Yang Lei

Chung-Shi Liu

Chen-Hua Douglas Yu

Ching-Hua Hsieh

Cheng-Yu Kuo

Hung-Jui Kuo

Wei-Jie Huang

Alexander Kalnitsky

Hui-Jung Tsai

Chin-Yu Ku

Kuo-Chio Liu

Yun Chen Hsieh

Tai-Min Chang

Jyun-Siang Peng

Ching-Pin Yuan

Kuo-Pin Chang

Kai-Di Wu

Sheng-Pin Yang

De-Dui Liao

Yu-Ching Lo

Isaac Huang

Tsung Lung Huang

Hsi-Ching Wang

Wen-Chih Lin

Hao-Yi Tsai

Tin-Hao Kuo

Mirng-Ji Lii

Sen-Kuei Hsu

Chi-Hui Lai

Po-Yuan Teng

Kuo-Lung Pan

Ying-Cheng Tseng

Yu-Ren Chen

Szu-Yu Yeh

Chien-Hsun Lee

Tsung-Ding Wang

Chien Ling Hwang

Cheng-Chung Lin

Hao-Cheng Hou

Ying-Jui Huang

Jung-Wei Cheng

Zheng-Yi Lim

Kuan-Cheng Wang

A workpiece chuck includes a supporting platform, a vacuum system, and a gas permeable buffer layer. The supporting platform has a supporting surface for holding a workpiece thereon. The vacuum system is disposed under and in gas communication with the supporting platform. The gas permeable buffer layer is disposed over the supporting platform and covers the supporting surface, wherein a hardness scale of the gas permeable buffer layer is smaller than a hardness scale of the supporting platform.

Workpiece chuck, workpiece handling apparatus, manufacturing method of semiconductor package

A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

Lamination process, and manufacturing method of semiconductor package using a chuck

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Semiconductor structure having a conductive feature comprising an adhesion layer and a metal region over and contacting the adhesion layer

A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

Package structure and manufacturing method of package structure thereof

Chuck, lamination process, and manufacturing method of semiconductor package using the same

A polishing pad, a polishing apparatus and a method of manufacturing a semiconductor package using the same are provided. In some embodiments, a polishing pad includes a sub-pad portion and a top pad portion over the sub-pad portion. The top pad portion includes a plurality of grooves having a first width and a plurality of openings having a second width different from the first width, and the openings are located in a center zone of the polishing pad.

Polishing pad, polishing apparatus and method of manufacturing semiconductor package using the same

Process including a re-etching process for forming a semiconductor structure

Semiconductor structure and method of forming the same

A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Package structure and method of fabricating the same

A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.

Semiconductor package including dies having high-modulus dielectric layer and manufacturing method thereof

A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.

Method of manufacturing semiconductor structure

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Growing community of inventors

Taichung, Taiwan

Yi-Yang Lei