Nan Ya Printed Circuit Board Corporation

Yi-Tang Weng

Shing-Fun Ho

Wei-Hsin Lin

A packaging substrate is fabricated using two plating steps for respectively plating the gold-plating areas defined on two opposite sides of the substrate. Before plating, the gold-plating areas are defined by a layer of solder mask. By doing this, the plated gold layer will not overlap with the solder mask, thereby preventing peeling or reliability problems.

Method for fabricating a packaging substrate

A method for making a packaging substrate is provided. A thin copper seed layer is formed on a carrier plate. A first resist layer is coated on the thin copper seed layer. The first resist layer defines a wire layout of copper plating area. A layer of copper is then electroplated on the copper plating area to form the wire layout. After this, the first resist layer is stripped to expose the wire layout and the thin copper seed layer. A patterned second resist layer is formed on the wire layout. The patterned second resist layer defines the Ni/Au plating area of the wire layout. The copper seed layer that is not covered by the second resist layer is etched away. A third resist layer is stacked on the second resist layer and defines an Au-plating area of the I/O fingers. Using the third resist layer as a plating hard mask, a layer of Ni/Au layer is plated on the exposed area of the wires. After this step, the second and third resist layers are removed.

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Tao-Yuan, Taiwan

Yi-Tang Weng