Globalfoundries Inc.

International Business Machines Corporation

Yi Qi

Hsien-Ching Lo

Hui Zang

Ruilong Xie

Jianwei Peng

Wei Hong

Srikanth Balaji Samavedam

Yanping Shen

Laegu Kang

Michael Ganz

Puneet Khanna

Yongjun Shi

Sri Charan Vemula

Xusheng Kevin Wu

Ajey Poovannummoottil Jacob

Xunyuan Zhang

Chanro Park

Julien Frougier

Jun Zhu

Jerome Ciavatti

Vara Govindeswara Reddy Vakada

Kangguo Cheng

Edward J Nowak

Judson Robert Holt

Ning Duan

Peng Ji

Sipeng Gu

Manfred Eller

Catherine B Labelle

Hui Zhan

Alina Vinslava

Vara G Reddy Vakada

Nicolas J Loubet

Haiting Wang

Wei Peng Huang

Qi Zhang

Min Gong

Jody Alan Fronheiser

Yu Ying Wang

Zhenyu Hu

Timothy James McArdle

Junchi Yan

George Robert Mulfinger

Shurong Liang

Guoqiang Hu

Jae Gon Lee

Liu Jiang

Tenko Yamashita

John H Zhang

Xiuyu Cai

Min Gyu Sung

Ying Liu

Siva P Adusumilli

Hong Yu

Steven J Bentley

Jiehui Shu

Shao Chun Li

Shesh Mani Pandey

Chun-Chen Yeh

Haigou Huang

Murat Kerem Akarvardar

Joseph Francis Shepard, Jr

Roderick Alan Augur

Sheng Huang

Kwan-Yong Lim

Lei Sun

Andreas Knorr

Josef S Watts

Randy W Mann

David Paul Brunco

Steven R Soss

Guowei Xu

Chun Yu Wong

El Mehdi Bazizi

Nigel Graeme Cave

Qian Zhao

Qun Gao

Xing Zhang

Sylvie M Mignot

Jeffrey Chee

Pei Zhao

Steffen A Sichler

Jianghu Yan

Edward Reis

Yong Jun Shi

Sang Woo Lim

Ömür I Aydin

Dongil Choi

James Psillas

Kyung-Bum Koo

Ju Yuan

Ming Lou

Emilie M S Bourjot

Yoong Hooi Yong

Joo Tat Ong

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a non-planar channel region is formed having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first semiconductor layer and the second semiconductor layer. Forming the non-planar channel region can include forming a nanosheet stack over a substrate, forming a trench by removing a portion of the nanosheet stack, and forming a third semiconductor layer in the trench. Outer surfaces of the first semiconductor layer, the second semiconductor layer, and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

A method and apparatus for parallelization of data processing. The method including: parsing a data processing flow to split a write table sequence for the data processing flow; generating a plurality of instances of the data processing flow based at least in part on the split write table sequence; and scheduling the plurality of instances for parallelization of data processing.

Parallelization of data processing

The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

Faceted epitaxial source/drain regions

One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

FinFET device with a wrap-around silicide source/drain contact structure

Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

Field-effect transistors with a grown silicon-germanium channel

The present disclosure relates to semiconductor structures and, more particularly, to cut margin structures and methods of manufacture. The method includes: forming a plurality of patterned hardmask stacks containing at least a semiconductor layer and a capping layer; removing a portion of a first patterned hardmask stack and a margin of an adjacent hardmask stack of the plurality of the patterned hardmask stacks; and selectively growing material on the margin of the adjacent hardmask stack.

Repaired mask structures and resultant underlying patterned structures

Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

Fin-type transistors with spacers on the gates

Described herein are nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects described include nanosheet-FET structures having an air gap as a bottom isolation area to reduce parasitic S/D leakage to the substrate.

Wrap-all-around contact for nanosheet-FET and method of forming same

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

Field-effect transistors with improved dielectric gap fill

A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

Transistor device structures with retrograde wells in CMOS applications

A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

Epitaxial region for embedded source/drain region having uniform thickness

Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

Metal-insulator-metal capacitors with enlarged contact areas

A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

Multiple gate length device with self-aligned top junction

A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

Transistors with H-shaped or U-shaped channels and method for forming the same

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Niskayuna, NY, United States of America

Yi Qi