Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Ming Sheu

Tsung-Hsing Yu

Zhiqiang Wu

Shin-Jiun Kuang

Chung-Cheng Wu

Carlos H Diaz

Ken-Ichi Goto

Wen-Hsing Hsieh

Chun-Fu Cheng

Chih-Ching Wang

Shih-Syuan Huang

Ying-Keung Leung

Da-Wen Lin

Chia-Wen Liu

Yi-Han Wang

Chih-Hao Wang

Hung-Li Chiang

Chun-Hsiung Lin

Jon-Hsu Ho

Ching-Fang Huang

Huan-Sheng Wei

Syun-Ming Jang Jang

Fu-Liang Yang

Tzer-Min Shen

Hong-Shen Chen

Kuan-Lun Cheng

Hun-Jan Tao

Chun-Yi Lee

Chih-Pin Tsao

Wen-Yuan Chen

Chi-Hsun Hsieh

Cheng-Ku Chen

Po-Ying Yeh

Shi-Shung Peng

Hsien-Wei Chen

Shin-Puu Jeng

Hao-Yi Tsai

Jiann-Tyng Tzeng

Kong-Beng Thei

Chih Chieh Yeh

Charles Chew-Yuen Young

Kam-Tou Sio

Ka-Hing Fung

Chih-Chieh Yeh

Harry Hak-Lay Chuang

Yo-Sheng Lin

Chu-Yun Fu

Sheng-Chen Chung

Krishna Kumar Bhuwalka

Shui-Ming Cheng

Sheng-Jier Yang

Chih-Chiang Wang

Yi-Ling Chan

Ying-Shiou Lin

Wan-Yih Lien

Anson Wang

Chung-Heng Yang

Kuan Lun Cheng

A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Method of fabricating a multi-gate device

The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

Structure and method for integrated circuit

A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

Semiconductor device and manufacturing method thereof

A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Multi-gate device

Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction. The fin-like semiconductor layer includes a third semiconductor material that is configured differently than the first semiconductor material.

Horizontal gate all-around device having wrapped-around source and drain

Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation.

Method for manufacturing semiconductor structure

The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

Structure and formation method of semiconductor device structure

The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

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Hsinchu, Taiwan

Yi-Ming Sheu