Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Ling Chan

Fu-Liang Yang

Chenming Hu

Kuo-Nan Yang

Hou-Yu Chen

Haur-Ywh Chen

You-Lin Chu

Carlos H Diaz

Da-Wen Lin

Yi-Ming Sheu

Fang-Cheng Chen

Wan-Yih Lien

Yi Ming Sheu

A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

Method of fabricating a necked FINFET device

The problem of gate oxide damage as a result of electrostatic discharges has been overcome by including within the drain of the ESD protection device a region having very high defect density. Its depth within the drain is such that no action occurs when applied voltages are low. However, when a high voltage is applied, the depletion layer grows wide enough to touch this region thereby allowing substantial current flow into the substrate which results in lowering the voltage to a safe level. The high defect density region is formed through ion implantation of relatively heavy ions such as germanium. This is done after completion of the normal manufacturing process including SALICIDATION, no significant heating of the device after that being permitted.

Electrostatic discharge device protection structure

A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a < > crystallographic orientation is bonded to the surface of a second silicon substrate having a < > crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a < > crystallographic orientation is bonded to the surface of a second silicon substrate having a < > crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement

A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions

A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P&plus; (or N&plus; in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.

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Miaoli, Taiwan

Yi-Ling Chan