Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Kan Cheng

Hsiao-Shu Chao

Jui-Feng Kuan

Po-Hsiang Huang

Lee-Chung Lu

Chin-Chou Liu

Hui Yu Lee

Chung-Hsing Wang

Fong-yuan Chang

Chi-Wen Chang

Fong-Yuan Chang

Ke-Ying Su

Huang-Yu Chen

Yuan-Te Hou

Cheng-Hung Yeh

Li-Chun Tien

Wen-Ju Preet Yang

Sheng-Hsiung Chen

Ru-Gun Liu

Ya Yun Liu

Hui-Zhong Zhuang

Wen-Hao Chen

Chi-Yu Lu

Pin-Dai Sue

Chin-Chang Hsu

Yung-Chin Hou

Wei-Yi Hu

Ching-Shun Yang

Ka Fai Chang

Chih-Ming Lai

Jiann-Tyng Tzeng

Gwan Sin Chang

Chin-Her Chien

Jung-Chou Tsai

Kuo-Nan Yang

Kam-Tou Sio

Sen-Bor Jan

Chih Ming Yang

Feng Wei Kuo

Tsong-Hua Ou

Chun-Chen Chen

Cheng-I Huang

Shao-Huan Wang

Hui-Yu Lee

Chin-Sheng Chen

Tsun-Yu Yang

Chin-Yuan Huang

Wei-Cheng Lin

Jerry Chang-Jui Kao

Tao Wen Chung

Yen-Hung Lin

Meng-Kai Hsu

Yao-Ching Ku

Ying-Chou Cheng

Chin-Hsiung Hsu

Ho Che Yu

XinYong Wang

Chia-Ming Ho

Ze-Ming Wu

Ying-Yu Shen

Chin-chou Liu

Chau-Wen Wei

Ming-Fa Chen

Wen-Shen Chou

Hiranmay Biswas

Chin-Hua Wen

Chung-Min Fu

Cliff Hou

Chung-Kai Lin

Kumar Lalgudi

Shang-Wei Fang

Chin-Cheng Kuo

Hung Lung Lin

Fang-Yu Fan

Shih-Wei Peng

Fu-Lung Hsueh

Dian-Hau Chen

Ken-Hsien Hsieh

Ta-Pen Guo

Wen-Chun Huang

Ting Yu Chen

Shun Li Chen

Chen-Lin Yang

Hsien-Hsin Sean Lee

Keh-Jeng Chang

Wen-Li Cheng

Chien-Ying Chen

Zhe-Wei Jiang

Ching Fu Chang

Jyun-Hao Chang

Yi-Chuin Tsai

Ching-Yu Huang

Kai-Ming Liu

Yih-Yuh Doong

Chun-Hui Tai

Kai-Yun Lin

Chu-Fu Chen

Hsiang-Ho Chang

HungLung Lin

An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage. The first and fourth via structures are configured to electrically connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure configured to carry the other of the power supply voltage or the reference voltage.

Integrated circuit having hybrid sheet structure

A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

SOIC chip architecture

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method and system for generating layout diagram including wiring arrangement

In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

Backside signal routing

An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

Integrated circuit with mixed row heights

The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Through-silicon via in integrated circuit packaging

A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

System and method for generating layout diagram including wiring arrangement

A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Method of forming merged pillar structures and method of generating layout diagram of same

A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.

Method and system of forming integrated circuit

An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mrow extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mrow are grouped into a first group, a second group and an ngroup extending along the second direction. The second pads in each of the first row, the second row and the mrow are grouped into a first group, a second group and an ngroup extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nconductive lines.

Interconnect structure and method for forming the same

A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Method for manufacturing a cell having pins and semiconductor device based on same

Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Semiconductor device and method of manufacture

A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

Hybrid sheet layout, method, system, and structure

A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

System for generating layout diagram including wiring arrangement

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method for generating layout diagram including wiring arrangement

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Taipei, Taiwan

Yi-Kan Cheng