Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Hang Lin

Jing-Cheng Lin

Jui-Pin Hung

Tsan-Hua Tung

Po-Hao Tsai

Li-Hui Cheng

Shin-Puu Jeng

Po-Yao Lin

Shu-Shen Yeh

Chin-Hua Wang

Po-Chen Lai

Che-Chia Yang

Kuang-Chun Lee

Min-Chen Lin

A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

Chip package structure with ring structure and method for forming the same

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Methods of packaging semiconductor devices including placing semiconductor devices into die caves

A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back surface opposite to the front surface. The back surface is in direct contact with the adhesive layer. A first maximum length of the adhesive layer is less than a second maximum length of the chip. The method includes forming a molding compound layer surrounding the chip and the adhesive layer. A first bottom surface of the adhesive layer is substantially coplanar with a second bottom surface of the molding compound layer. The method includes forming a redistribution structure over the chip and the molding compound layer.

Method for forming chip package structure with adhesive layer

A chip package structure is provided. The chip package structure includes a redistribution structure. The chip package structure includes a first chip over the redistribution structure. The first chip has a front surface and a back surface opposite to the front surface, and the front surface faces the redistribution structure. The chip package structure includes an adhesive layer on the back surface. The adhesive layer is in direct contact with the back surface, and a first maximum length of the adhesive layer is less than a second maximum length of the first chip. The chip package structure includes a molding compound layer over the redistribution structure and surrounding the first chip and the adhesive layer. A first top surface of the adhesive layer is substantially coplanar with a second top surface of the molding compound layer.

Chip package structure with adhesive layer

Methods of packaging semiconductor devices and structures thereof

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure.

Adhesion between post-passivation interconnect structure and polymer

Growing community of inventors

Hsinchu, Taiwan

Yi-Hang Lin