Intel Corporation

Yi Elyn Xu

Florence R Pon

Hyoung Il Kim

Yuhong Cai

Bilal Khalaf

Min-Tih Ted Lai

Sireesha Gogineni

Dennis Sean Carr

Yong She

Leo J Craft

James Jian Zhang

Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.

Pad design for thermal fatigue resistance and interconnect joint reliability

A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.

Multi-die, vertical-wire package-in-package apparatus, and methods of making same

Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.

Embedded component and methods of making the same

Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.

Bowl shaped pad

Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.

Temporary interconnect for use in testing a semiconductor package

A semiconductor structure is disclosed. The semiconductor structure includes a substrate an elastomer coupled to the substrate and a plurality of bondfingers on the elastomer. The substrate, the elastomer and the bondfingers are configured to cooperatively expand and retract.

Shrinkable package assembly

Embodiments described herein provide techniques for using a stress absorption material to improve solder joint reliability in semiconductor packages and packaged systems. One technique produces a semiconductor package that includes a die on a substrate, where the die has a first surface, a second surface opposite the first surface, and a sidewall surface coupling the first surface to the second surface. The semiconductor package further includes a stress absorption material contacting the sidewall surface of the die and a molding compound separated from the sidewall surface of the die by the stress absorption material. The Young's modulus of the stress absorption material is lower than the Young's modulus of the molding compound. One example of a stress absorption material is a photoresist.

Semiconductor package design for solder joint reliability

Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.

Diode for use in testing semiconductor packages

Embodiments described herein provide techniques for forming a solder mask having a repeating pattern of features formed therein. The repeating pattern of features can be conceptually understood as a plurality of groove structures formed in the solder mask. The solder mask can be included in a semiconductor package that comprises the solder mask over a substrate and a molding compound over the solder mask that conforms to the repeating pattern of features. Several advantages are attributable to embodiments of the solder mask described herein. One advantage is that the repeating pattern of features formed in the solder mask increase the contact area between the solder mask and the molding compound. Increasing the contact area can assist with increasing adherence and conformance of the molding compound to the solder mask. This increased adherence and conformance assists with minimizing or eliminating interfacial delamination.

Solder mask design for delamination prevention

An integrated circuit structure may be fabricated having a first integrated circuit package comprising a first integrated circuit device electrically attached to a first surface of a first substrate, a second integrated circuit package comprising a second integrated circuit device electrically attached to a first surface of a second substrate and an opening extending between a first surface of the second substrate and the second surface of the second substrate, and an interconnection structure electrically attached to the first surface of the first substrate, wherein a portion of the interconnection structure extends into the second substrate opening and wherein the interconnection structure is electrically attached to a first surface of the second substrate.

Interposer for electrically connecting stacked integrated circuit device packages

Semiconductor packages including active die stacks, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes an active die having a top surface covered by a molding compound, and a bonding pad attached to only one interconnect wire. A method of fabricating the semiconductor package includes bridging a pair of dies stacks by the interconnect wire, and dividing the interconnect wire to form separate wire segments attached to respective die stacks.

Semiconductor package having singular wire bond on bonding pads

An apparatus is provided which comprises: a substrate; a stacked ring structure disposed on the substrate, the stacked ring structure comprising a first ring and a second ring; a first partial through-mold-via (TMV) formed on the first ring; and a second partial TMV formed on the second ring, wherein the first ring and the second ring are stacked such that the first partial TMV is aligned on top of the second partial TMV.

Through mold via (TMV) using stacked modular mold rings

Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments. In embodiments, a package assembly includes a die and a mold compound disposed on the die, to encapsulate the die. The package may further include a thermal solution including one or more thermal fins attached to the mold compound at their respective ends. The thermal fins may be disposed substantially flat on a top surface of the mold compound at a first temperature, and rise away from the top surface of the mold compound in response to a change of temperature to a second temperature, to reach an enclosure that surrounds the package assembly, to provide direct heat conductivity between the die and the enclosure. The second temperature may be greater than the first temperature. Other embodiments may be described and/or claimed.

Semiconductor package with thermal fins

An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

Growing community of inventors

Folsom, CA, United States of America

Yi Elyn Xu