Altera Corporation

Yew Fatt Kok

Chooi Pei Lim

Kar Keng Chua

Joo Ming Too

Kok Heng Choe

Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Clock signal networks for structured ASIC devices

Techniques are provided for controlling an on-chip termination (OCT) in an output driver. The OCT control circuit calibrates the effective resistance of transistors in the output driver to match an external resistor using a feedback loop. The feedback loop monitors the output voltage and generates an analog calibration signal that varies the output impedance of a selected group of the output transistors that are enabled to drive the output terminal. Digital signals under the control of the user select the number of output transistors to be enabled based on the output driver requirements of the circuit. The analog calibration signal varies the signal level driving the selected output transistors to modify the effective output impedance of the circuit for better termination matching.

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Penang, Malaysia

Yew Fatt Kok