Samsung Electronics Co., Ltd.

Yeoncheol Heo

Mirco Cantoro

Dong Il Bae

Maria Toledano Luque

Kwanyoung Chun

Sharma Deepak

The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

Field effect transistor including multiple aspect trapping ratio structures

A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.

Method of fabricating a semiconductor device including vertical-type field effect transistors

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

Semiconductor device including an active pattern having a lower pattern and a pair of channel patterns disposed thereon and method for manufacturing the same

A semiconductor device may include a substrate, a first doped region and a second doped region on the substrate, a base region on the first doped region, a channel region on the second doped region, and a third doped region and a fourth doped region on the base region and the channel region, respectively. The first doped region and the second doped region may be isolated from direct contact with each other in a first direction that is substantially parallel to a top surface of the substrate. A channel gate structure may be on a side surface of the channel region. A thickness of the base region, in a second direction that is substantially perpendicular to the top surface of the substrate, may be equal to or larger than a thickness of the channel region.

Semiconductor devices and methods of fabricating the same

Method for manufacturing a semiconductor device including a pair of channel semiconductor patterns

Semiconductor devices including separate doped regions

Semiconductor device including vertical-type field effect transistors and method of fabricating the same

A semiconductor device includes a semiconductor substrate including a first source/drain region formed in an upper portion of the semiconductor substrate, a metal silicide layer that covers a top surface of the first source/drain region, and a semiconductor pillar that penetrates the metal silicide layer and is connected to the semiconductor substrate. The semiconductor pillar includes a second source/drain region formed in an upper portion of the semiconductor pillar, a gate electrode on the metal silicide layer, with the gate electrode surrounding the semiconductor pillar in a plan view. A contact is connected to the metal silicide layer.

Vertical transistor having a semiconductor pillar penetrating a silicide formed on the substrate surface

Field effect transistor including multiple aspect ratio trapping structures

A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.

Growing community of inventors

Suwon-si, South Korea

Yeoncheol Heo