Samsung Electronics Co., Ltd.

Yeo-Hoon Yoon

Jae Choon Kim

Jichul Kim

KyongSoon Cho

Hansung Ryu

YoungSang Cho

Sun-Won Kang

Ho-Jeong Moon

Se-Young Yang

A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

Semiconductor packages

Semiconductor packages having redistribution substrate

Provided is a method for testing adhesion. The method includes forming thin films on a substrate; attaching an elastic plate to the substrate, wherein the elastic plate has a larger elastic coefficient than the substrate; and performing an adhesion test on the thin films using an adhesion test apparatus.

Adhesion test method using elastic plate

Integrated circuit packages include an integrated circuit mounting substrate having a hole that defines an inner wall of the integrated circuit mounting substrate. An integrated circuit is provided in the hole. A sinuous lead frame extends from the integrated circuit and is connected to the inner wall. The sinuous lead frame extends back and forth along a given direction, and may include a U- and/or V-shape, and round and/or jagged portions. Related packaging methods are also disclosed.

Integrated circuit packages including sinuous lead frames

Growing community of inventors

Yongin-si, South Korea

Yeo-Hoon Yoon