United Microelectronics Corp.

Yen-Hsueh Huang

Yu-Tse Kuo

Chun-Yen Tseng

Shih-Chin Lin

Chung-Cheng Tsai

Chih-Wei Tsai

Tsan-Tang Chen

Chang-Ting Lo

Pei-Geng Ma

An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.

Static random access memory device with keeper circuit

In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.

Hidden refresh method and operating method for pseudo SRAM

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Taipei, Taiwan

Yen-Hsueh Huang