Intel Corporation

Yen-Cheng Liu

Krishnakanth Venkata Sistla

Bahaa Fahim

Robert G Blankenship

Vedaraman Geetha

Jeffrey D Chamberlain

Ganapati Srinivasa

Herbert H Hum

Stephen R Van Doren

Raj K Ramanujan

Christopher J Hughes

Debendra Das Sharma

Arvind A Kumar

Venkatraman Iyer

Simon P Johnson

Robert J Safranek

Darren S Jue

Ashish Gupta

Jeffrey Charles Swanson

Aaron T Spink

Fulvio Spagna

Rahul R Shah

Robert H Beers

Jeff Willey

Sitaraman V Iyer

William Harry Nale

Rajesh M Sankaran

Ankush Varma

Joseph Nuzman

David A Koufaty

Samantika S Sury

Doddaballapur N Jayasimha

Adrian C Moga

Mahesh K Kumashikar

Jonas Svennebring

Geeyarpuram N Santhanakrishnan

Dheeraj R Subbareddy

Gerald S Pasdast

George Zacharias Chrysos

William R Halleck

Zhong-Ning George Cai

Bongjin Jung

Jeffrey D Gilbert

Nevine Nassif

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

Zeshan A Chishti

Swadesh Choudhary

Aamer Jaleel

Gilbert A Neiger

Mohan J Kumar

Wei P Chen

Christian Maciocco

Sailesh Kumar

Alexander W Min

Jr-Shian Tsai

Sridhar Muthrasanallur

Jong Soo Park

Kenneth C Creta

Sailesh Kottapalli

Niall D McDonnell

Mesut A Ergin

Larisa Novakovsky

James R Vash

Rahul Pal

Namakkal N Venkatesan

Stephen J Robinson

Eswaramoorthi Nallusamy

Ian A Young

Glenn J Hinton

Uygar E Avci

Tanay Karnik

Richard A Uhlig

Min Huang

Mark A Schmisseur

Ravishankar Iyer

Sreenivas Subramoney

Sanjay Kumar

Bill Nale

Daniel Henry Morris

Kai Cheng

Robert S Chappell

Stephen T Palermo

Brian S Morris

Theodros Yigzaw

Edwin Verplanke

Rupin H Vakharwala

Jose Andy Vargas

Eric R Delano

Julius Yuli Mandelblat

Brinda Ganesh

Ishwar Agarwal

Ajaya V Durg

Huichu Liu

Subramanya R Dulloor

Kaushik Vaidyanathan

Nazar Syed Haider

Gunnar Gaubatz

Anand K Enamandram

In an embodiment, a processor may include an execution engine to execute a plurality of instructions, a memory to store a tagged data structure comprising a plurality of entries, and an eviction circuit. The eviction circuit may be to: generate a pseudo-random number responsive to an eviction request for the tagged data structure; in response to a determination that the pseudo-random number is outside of a valid eviction range for the plurality of entries, generate an alternative identifier by rotating through the valid eviction range, the valid eviction range comprising a range of numbers that are valid to identify victim entries of the tagged data structure; and evict a victim entry from the tagged data structure, the victim entry associated with the alternative identifier. Other embodiments are described and claimed.

Selection of victim entry in a data structure

Examples described herein relate to programming a memory rule for a home agent, wherein the programming a memory rule for a home agent comprises: receiving at least one memory rule programming and based on a cluster associated with the home agent, configuring a memory rule register using a memory rule programming from among the at least one memory rule programming. In some examples, receiving at least one memory rule programming includes receiving a first memory rule programming and receiving a second memory rule programming. In some examples, a mask is applied to reject the first memory rule programming; and applying the mask to accept the second memory rule programming and program the memory rule for the home agent.

Technologies for configuration of memory ranges

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

Flexible on-die fabric interface

Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.

Link affinitization to reduce transfer latency

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Multiple dies hardware processors and methods

Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Accessing a memory using index offset information

Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes&#x2014;first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is 'primary' and other is called the 'assist'. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

Low overhead, high bandwidth re-configurable interconnect apparatus and method

A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

Redundant cache-coherent memory fabric

Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Remote atomic operations in multi-socket systems

Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Processor and method implementing a cacheline demote machine instruction

Growing community of inventors

Portland, OR, United States of America

Yen-Cheng Liu