Cadence Design Systems, Inc.

Yee-Wing Hsieh

Manish Pandey

Angela Krstic

Andy Lin

Marcelo Glusman

Marcalo Glusman

Shan-Chyun Ku

A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.

Method and system for generating design constraints

Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.

Verifying multiple constraints for circuit designs

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Pleasanton, CA, United States of America

Yee-Wing Hsieh