Lucent Technologies Inc.

Psiloquest Inc.

Texas Instruments Corporation

Agere Systems Guardian Corp.

At+t Corp.

At&t Bell Laboratories

Yaw S Obeng

Edward M Yokley

Jiong-Ping Lu

Ping Jiang

Joe G Tran

Jennifer S Obeng

Freidoon Mehrad

Laurence D Schultz

Peter A Thomas

Scott Robert Summerfelt

Sanjeev Aggarwal

Mark R Visokay

William Graham Easter

Richard L Guldi

Theodore Sidney Moise

Francis Gabriel Celii

Lindsey H Hall

Robert Kraft

John Albert Maze, Iii

Kezhakkedath Ramunni Udayakumar

Susan Clay Vitkavage

David Charles Brady

Steven Alan Lytle

Kathleen Richardson

Juanita DeLoach

Anthony S Oates

Aaron L Frank

Ramaswamy Srinivasa Raghavan

Edward J Vajda

Murlidhar Bashyam

Randolph H Burton

Eric John Persson

Patrick J Kelly

Seung H Kang

Jia Sheng Huang

Srinivasa Raghavan

Robert L Opila

A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.

Method to attain low defectivity fully silicided gates

A method for making a transistorthat includes using a transition metal nitride layerand/or a SOG layerto protect the source/drain regionsfrom silicidation during the silicidation of the gate electrode. The SOG layeris planarized to expose the transition metal nitride layeror the gate electrodebefore the gate silicidation process. If a transition metal nitride layeris used, then it is removed from the top of the gate electrodebefore the full silicidation of the gate electrode

FUSI integration method using SOG as a sacrificial planarization layer

A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Method for cleaning post-etch noble metal residues

A method for manufacturing a semiconductor device. The method comprises forming a metal layer on a silicon-containing layer located on a semiconductor substrate. The method also comprises reacting a portion of the metal layer with the silicon-containing layer to form a metal silicide layer. The method further comprises removing an unreacted portion of the metal layer on the metal silicide layer by a removal process. The removal process includes delivering a flow of an acidic solution to a surface of the unreacted portion of the metal layer, wherein the acidic solution delivered to the surface is substantially gas-free.

Method for reliably removing excess metal during metal silicide formation

A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Method of manufacturing metal silicide contacts

The present invention is directed, in general, to a chemical mechanical polishing pad comprising a polishing body and a backing material coupled to the polishing body. The polishing body comprising a compacted thermoplastic foam substrate, wherein the compacted thermoplastic foam substrate has a density that is as at least about 1.1 times greater than an uncompacted thermoplastic foam substrate density. Other aspects of the invention comprise a method for manufacturing the above-described chemical mechanical polishing pad and chemical mechanical polishing apparatus comprising the chemical mechanical polishing pad.

Compacted polishing pads for improved chemical mechanical polishing longevity

The present invention is directed, in general, to a method of polishing a surface on substrates, such as semiconductor wafers and, more specifically, to a polishing pad suitable for this purpose. The polishing pad comprises a polishing body that includes a cross-linked polymer material, and may be incorporated into a polishing apparatus. Polishing includes positioning the substrate containing at least one layer against the polishing body and polishing the layer.

Selective chemical-mechanical polishing properties of a cross-linked polymer and specific applications therefor

The present invention provides, chemical mechanical polishing pad with improved polishing properties and longevity for polishing semiconductor wafers. The polishing pad comprises a thermoplastic backing film and a pressure sensitive adhesive coupled to the thermoplastic backing film. The pressure sensitive adhesive is configured to couple a chemical mechanical polishing pad to a polishing platen. The pressure sensitive adhesive is further configured to provide an interface capable of substantially preventing delamination of the polishing pad from the polishing platen for at least about 4 days exposure to a polishing slurry medium having a pH of about 4 or higher.

Polishing pad resistant to delamination

The present invention is directed to a method for preparing a polymer for chemical mechanical polishing of a semiconductor substrate. The method comprises providing a thermoplastic foam substrate and exposing the substrate to an initial plasma reactant to produce a modified surface thereon. The method also includes exposing the modified surface to a secondary plasma reactant to create a grafted surface on the modified surface. An electrode temperature is maintained between about 20&deg; C. and about 100&deg; C. during the exposures of the substrate and the modified surface.

Method for preparing a polymer for chemical mechanical polishing

The present invention is directed, in general, to a method of planarizing a surface on a semiconductor wafer and, more specifically, to a method of altering the properties of polishing pads to improve thermal management during chemical-mechanical planarization, the resulting heat conductive pad and a polishing apparatus that includes the pad. The pad includes a polishing body composed of a thermoconductive polymer comprising an substrate and filler particle containing a Group II salt and within the substrate.

Thermal management with filled polymeric polishing pads and applications therefor

The present invention is directed, in general, to packaged polishing pads for chemical mechanical polishing of semiconductor wafers and integrated circuits. More specifically, the invention is directed to a method of preparing and packing the pad and the packaging therefor. Prior to placing the pad on a platen and polishing with the pad, a polishing pad having an hygroscopic absorbency is soaked with an aqueous media for a time sufficient to equilibrate the pad. The pad maybe packaged by placement in a sealable moisture tight package after soaking or before soaking along with a sufficient quantity of aqueous media to allow the pad to equilibrate.

Polishing pad composition and method of use

The present invention provides, polishing pad with improved polishing properties and longevity. The pad is comprised of a thermoplastic foam substrate having a surface comprised of concave cells. A polishing agent coats an interior surface of the concave cells. The invention includes a method for preparing the polishing pad, and a polishing apparatus comprising the polishing pad.

Polishing pad support that improves polishing performance and longevity

To address the deficiencies of the prior art, the present invention provides a polishing pad comprising a thermoplastic polymer and a method of manufacturing therefor. More specifically, the present invention polishing pad fabricated from an extruded amorphous thermoplastic and free of a gate vestige. The invention also provides a method of manufacturing a polishing pad that is free from a gate vestige pad from an extruded amorphous thermoplastic.

Substrate polishing device and method

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Orlando, FL, United States of America

Yaw S Obeng