Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Fuji Electric Holdings Co., Ltd.

Yasushi Niimura

Takeyoshi Nishimura

Masanori Inoue

Toshiaki Sakata

Takashi Kobayashi

Hitoshi Abe

Shunji Takenoiri

Tatsuhiko Fujihira

Yasuhiko Onishi

Takumi Fujimoto

Hidenori Takahashi

Sota Watanabe

Takamasa Wakabayashi

Shuhei Tatemichi

Takayuki Shimatou

Toshihiro Arai

Hideki Shishido

Tadanori Yamada

To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including:

Assessment method, and semiconductor device manufacturing method

To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including: acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

A first parallel pn layer having a first n-type region and a first p-type region junctioned alternately and repeatedly is disposed in an element active portion. The first parallel pn layer has a striped planar layout. A second parallel pn layer having a second n-type region and a second p-type region junctioned alternately and repeatedly is disposed in a high voltage structure. The second parallel pn layer has a striped planar layout in a direction identical to that of the first parallel pn layer. An intermediate region having a third parallel pn layer and a fourth parallel pn layer of a lower impurity quantity than the first parallel pn layer is disposed between the first and second parallel pn layers, and formed by diffusing impurity implanting regions becoming the first and the second parallel pn layers formed separated from each other to a region in which no impurity is ion-implanted.

Semiconductor device

A first parallel pn layer in which first n-type regions and first p-type regions are disposed in a plan view layout of stripes in an element active portion. A second parallel pn layer has a plan view layout of stripes oriented in the same direction as that of the stripes of the first parallel pn layer in a breakdown voltage structure portion. Corner portions of the first parallel pn layer has a plan view shape where stepped regions formed by shortening the length of the first n-type and p-type regions in steps are disposed in a stepwise arrangement. The stepped regions continue with a second parallel pn layer via an intermediate region lower in average impurity concentration than the first parallel pn layer.

Semiconductor device manufacturing method

Semiconductor device and semiconductor device manufacturing method

Semiconductor device and manufacturing method of semiconductor device

An ndrift layer is a parallel pn layer having an n-type region and a p-type region are alternately arranged in the direction parallel to the main surface so as to come into contact with each other, and have a width in a direction parallel to the main surface of the substrate which is less than a length in a direction perpendicular to the main surface of the substrate. A second-main-surface-side lower end portion of the p-type region has a structure in which a high-concentration lower end portion and a low-concentration lower end portion of a p-type low-concentration region are repeated at a predetermined pitch in the direction parallel to the main surface of the substrate. It is possible to provide a super junction MOS semiconductor device which can improve a trade-off relationship between turn-off loss and turn-off dv/dt and improve avalanche resistance.

Semiconductor device and semiconductor device fabrication method

A MOS semiconductor device has a MOS structure, including a pregion that surrounds an n-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n-type source region and a surface layer of an nlayer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

Semiconductor device and method for manufacturing semiconductor device

A screen oxide film is formed on an n&#x2212; drift layer () that is disposed on an anterior side of an n-type low-resistance layer (), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film () is formed. N-type impurity ions at a concentration higher than that of the n&#x2212; drift layer are implanted through the nitride shielding film () from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer () is formed. The screen oxide film is removed. A gate oxide film () is formed. A gate electrode () is formed on the gate oxide film (). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, p&#x2212; well regions () are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, n source regions () are formed.

Manufacturing method of semiconductor apparatus and semiconductor apparatus

A semiconductor device manufacturing method is disclosed by which electron beam irradiation is accomplished at a low cost while exhibiting uniform characteristics. A wafer stack consisting of multiple stacked wafers is irradiated with an electron beam from both the front surface and reverse surface. As such, a semiconductor device manufacturing method is provided whereby the electrical characteristics are extremely uniform between wafers, and costs are reduced by reducing the number of electron beam irradiations.

Semiconductor device and manufacturing method therefor

Aspects of the invention are directed to a vertical semiconductor device including an element active portion and a voltage withstanding structure portion that has a first main electrode and a gate pad electrode on a first main surface of the element active portion, includes first parallel pn layers in a drift layer below the first main electrode, and includes second parallel pn layers below the gate pad electrode. The vertical semiconductor device includes a first conductivity type isolation region between the second parallel pn layers below the gate pad electrode and a p-type well region disposed in a surface layer of the drift layer, and by the repetition pitch of the second parallel pn layers being shorter than the repetition pitch of the first parallel pn layers, it is possible to obtain low on-state resistance, high avalanche withstand, high turn-off withstand, and high reverse recovery withstand.

Vertical semiconductor device including element active portion and voltage withstanding structure portion, and method of manufacturing the vertical semiconductor device

A screen oxide film is formed on an n-drift layer () that is disposed on an anterior side of an n-type low-resistance layer (), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film () is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film () from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer () is formed. The screen oxide film is removed. A gate oxide film () is formed. A gate electrode () is formed on the gate oxide film (). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, p- well regions () are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, n source regions () are formed.

A screen oxide film is formed on an n&#x2212; drift layer () that is disposed on an anterior side of an n-type low-resistance layer (), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film () is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film () from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer () is formed. The screen oxide film is removed. A gate oxide film () is formed. A gate electrode () is formed on the gate oxide film (). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, p&#x2212; well regions () are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, n source regions () are formed.

Growing community of inventors

Matsumoto, Japan

Yasushi Niimura