Nec Corporation

Oki Electric Industry Co., Ltd.

Nippon Telegraph and Telephone Public Corporation

Yasuo Ohno

Yuji Takahashi

Kazuaki Kunihiro

Kensuke Kasahara

Hironobu Miyamoto

Yuji Ando

Tatsuo Nakayama

Masaaki Kuzuhara

Nobuyuki Hayama

Kouji Matsunaga

Kohji Matsunaga

Satoru Ohkubo

Hiroshi Tanabe

Noriaki Matsuno

Masahiro Fujii

Tadashi Maeda

Naotaka Iwata

Nobuhide Yoshida

Keiichi Numata

Kotaro Kato

Haruo Mori

Koji Matsunaga

Yutaka Ohta

Takao Atsumo

Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances

A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Hetero-junction field effect transistor having an intermediate layer

A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Semiconductor device with schottky electrode having high schottky barrier

A p-type layer and an n-type layer which constitute a barrier layer are provided, and a leak of the holes at the time of the negative bias accompanying the p-type layer buffer required for the higher tolerance voltage is suppressed, and the discharge of the holes at the positive bias can be efficiently carried out. The tolerance voltage at the time of the OFF state is raised at the p-type layer buffer, and the tolerance voltage at the time of the ON state at the discharge of the holes is raised. Since no leak is generated from the p-type layer, the drain current is not lowered, and a higher output can be realized both in terms of the current and in terms of the voltage.

Field effect transistor with barrier layer to prevent avalanche breakdown current from reaching gate and method for manufacturing the same

A semiconductor device of the present invention comprises Al Ga N layer and Al Ga N layer having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al Ga N layer is formed is used as a low resistance area, while an area where Al Ga N layer is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Semiconductor device

In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

Method of manufacturing semiconductor device with sidewall metal layers

An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode a source electrode and a drain electrode are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20&deg; with respect to a C axis of sapphire.

Semiconductor device having drain and gate electrodes formed to lie along few degrees of direction in relation to the substrate

A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.

Compound semiconductor field effect transistor

A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer. Impurity concentration N2 and thickness D of the second conductivity layer are such that the following relationship holds:

Field-effect transistor and method for manufacturing the field effect transistor

There are provided a compound semiconductor device having a semiconductor multilayered structure, and a method of manufacturing the same. The semiconductor multilayered structure consists of a first recess etching stopper formed on a conductive layer of a compound semiconductor, a first semiconductor layer formed on the first recess etching stopper layer, a second recess etching stopper layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second recess etching stopper layer.

Compound semiconductor device and method of manufacturing the same

A p-type layer which is not depleted is inserted in a position at a depth relative to a lower surface of a gate electrode that is less than three times the distance between a lower surface of a gate electrode and a channel layer. A drain voltage at which the p-type layer is depleted is higher than a drain voltage at which a speed of electrons is saturated for thereby shielding traps while suppressing a drain parasitic capacitance and a short channel effect.

Compound semiconductor field-effect transistor with improved current

A method of evaluating the surface/interface of a semiconductor device is disclosed. This method uses the semiconductor device in which an n-type source electrode and an n-type drain electrode are formed on both ends of the surface of an n-type conductive layer formed on a semiconductor substrate; and a gate electrode composed of a p-type ohmic electrode or an n-type Schottky electrode is formed on one end of the surface on which the source or drain electrode is not disposed. In this semiconductor device, voltage to be applied to the gate electrode is changed and a change of current flowing between the source electrode and the drain electrode in response to the voltage change is measured. Then the type of trap on the surface/interface of the semiconductor is determined from an amount of change in the value of the current.

Method of evaluating the surface state and the interface trap of a

In a field effect transistor, a semiconductor channel layer is formed for carriers to run therein, and a first conductive semiconductor carrier supply layer is formed on the channel layer. Also, a second conductive semiconductor layer has a conductive type opposite to the carrier supply layer or contacts the gate electrode and is formed of same materials as the carrier supply layer. A third conductive semiconductor layer is formed on the layer having a conductive type opposite to the carrier supply layer or contacting the gate electrode and has the same conductive type of the carrier supply layer. A schottky gate electrode is formed in contact with the second conductive semiconductor layer.

Field effect transistor with stabilized threshold voltage

A field-effect transistor has a source region, a drain region, a gate electrode, and a low resistivity layer. The source and drain regions are of a first conductivity type and formed as surface regions of a semiconductor layer formed on one of an insulating substrate and a semi-insulating substrate. The gate electrode is formed on a channel region between the source region and the drain region. The low resistivity layer serving as a shield layer is disposed underneath and spaced apart from the source, drain and channel regions, and overlaps the source region with an overlap area being larger than an overlap area between the low resistivity layer and the drain region. The arrangement enables the prevention of noise margin reduction and erroneous operation.

Method for forming a field-effect transistor having difference in

In a switching speed fluctuation detecting apparatus, an input terminal for receiving a signal having a definite time period, a series arrangement of at least one first logic circuit connected to the input terminal, a second logic circuit having a first input connected to the input terminal and a second input connected to an output of the series arrangement and an integrator connected to an output of the second logic circuit are provided.

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Tokyo, Japan

Yasuo Ohno